From 6fa08400a58f7073e1ca72ddb5738764963293d0 Mon Sep 17 00:00:00 2001 From: Riya Jain Date: Fri, 19 Apr 2024 01:16:27 +0530 Subject: [PATCH] feat: added reserved fields --- model/riscv_insts_base.sail | 2 +- model/riscv_types.sail | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 4261e8ccd..ff0e91d54 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -783,7 +783,7 @@ $[name "fence (instruction)"] union clause ast = FENCEI : unit mapping clause encdec = FENCEI() - <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111 + <-> reserved_bits_12(ZERO) @ reserved_bits_5(ZERO) @ 0b001 @ reserved_bits_5(ZERO) @ 0b0001111 /* fence.i is a nop for the memory model */ function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS } diff --git a/model/riscv_types.sail b/model/riscv_types.sail index 2b1c132ec..6152f780d 100644 --- a/model/riscv_types.sail +++ b/model/riscv_types.sail @@ -134,6 +134,10 @@ union AccessType ('a : Type) = { Execute : unit } +enum reserved_bits_enum = { ZERO } +mapping reserved_bits_5 : reserved_bits_enum <-> bits(5) = { ZERO <-> 0b00000 } +mapping reserved_bits_12 : reserved_bits_enum <-> bits(12) = { ZERO <-> 0b000000000000 } + enum word_width = {BYTE, HALF, WORD, DOUBLE} /* architectural interrupt definitions */