Tag register information with encapsulating extension(s)

[ThinkOpenly]

Registers are defined in the Sail code in various places. These definitions should only manifest if the encapsulating extension(s) are enabled, and it should be easily determined when parsing in which extension(s), if any, each register is encapsulated.

[AbhinavMir]

Looking into this!

[AbhinavMir]

Hi, I had started working on this but figured I needed some help.

Would the change only reflect in how the sail parser parses sail riscv or are we changing the sail riscv model to something like this?

// Define the extension
val ENABLE_EXTENSION_ZKNH : bool = true

// Define a register for the Zknh extension
if ENABLE_EXTENSION_ZKNH then {
  register regX : xlenbits
}

// Define an instruction that uses the register, only if the extension is enabled
if ENABLE_EXTENSION_ZKNH then {
  let sha256sig1(rs1 : regidx, rd : regidx) = {
    let inb : bits(32) = subrange_bits(rX_bits(rs1), 31, 0) in
    let result : bits(32) = xor_vec(rotater(inb, 17), xor_vec(rotater(inb, 19), shiftr(inb, 10))) in
    wX_bits(rd, sign_extend(64, result));
    RETIRE_SUCCESS
  }
}

[ThinkOpenly]

Would the change only reflect in how the sail parser parses sail riscv or are we changing the sail riscv model to something like this?

The goal is that the Sail parser/backends are ignorant, and all information is accurately and completely represented in Sail (and then in JSON).

// Define the extension
val ENABLE_EXTENSION_ZKNH : bool = true

Let utilize the extension function we've been using elsewhere, so you wouldn't need the above.

// Define a register for the Zknh extension
if ENABLE_EXTENSION_ZKNH then {
  register regX : xlenbits
}

So, the condition above would become extension("Zknh").

Does scoping allow this to work? The Sail language manual has no discussion on scoping, so maybe everything is at global scope?

// Define an instruction that uses the register, only if the extension is enabled
if ENABLE_EXTENSION_ZKNH then {

Same.

  let sha256sig1(rs1 : regidx, rd : regidx) = {
    let inb : bits(32) = subrange_bits(rX_bits(rs1), 31, 0) in
    let result : bits(32) = xor_vec(rotater(inb, 17), xor_vec(rotater(inb, 19), shiftr(inb, 10))) in
    wX_bits(rd, sign_extend(64, result));
    RETIRE_SUCCESS
  }
}

Going back to your original question:

are we changing the sail riscv model [...]?

Yes.

[AbhinavMir]

Makes sense! The code was more pseudocode less real code, just to get an idea. Working on this!