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In order to test with the single phase inverter perfboard all of the following are required.
Deadtime - we need to account for the rise and fall time of the gate driver and the transistor when switching from '0' to '1'
Variable Output Voltage - the test circuit will be much lower power when compared to the final VFD (+/- 3V, 100s of mA), we need to sample a different reference sine wave.
~60Hz operation frequency - the perfboard circuit will have a static cut-off frequency of ~70Hz, the operating frequency of the SPDM code should be selected to minimize harmonics in the resultant waveform.
The text was updated successfully, but these errors were encountered:
In order to test with the single phase inverter perfboard all of the following are required.
Deadtime - we need to account for the rise and fall time of the gate driver and the transistor when switching from '0' to '1'
Variable Output Voltage - the test circuit will be much lower power when compared to the final VFD (+/- 3V, 100s of mA), we need to sample a different reference sine wave.
~60Hz operation frequency - the perfboard circuit will have a static cut-off frequency of ~70Hz, the operating frequency of the SPDM code should be selected to minimize harmonics in the resultant waveform.
The text was updated successfully, but these errors were encountered: