a64fx_SME.yaml

# The following resources where utilised to create the config file and naming schemes:
# https://github.com/fujitsu/A64FX

Core:
  Simulation-Mode: outoforder
  ISA: AArch64
  Clock-Frequency-GHz: 1.8
  Timer-Frequency-MHz: 100
  Micro-Operations: True
  Vector-Length: 512
  Streaming-Vector-Length: 512
Fetch:
  Fetch-Block-Size: 32
  Loop-Buffer-Size: 48
  Loop-Detection-Threshold: 4
Process-Image:
  Heap-Size: 1073741824
  Stack-Size: 1048576
Register-Set:
  GeneralPurpose-Count: 96
  FloatingPoint/SVE-Count: 128
  Predicate-Count: 48
  Conditional-Count: 128
  SME-Matrix-Count: 2
  SME-Lookup-Table-Count: 8
Pipeline-Widths:
  Commit: 4
  FrontEnd: 4
  LSQ-Completion: 2
Queue-Sizes:
  ROB: 128
  Load: 40
  Store: 24
Port-Allocator:
  Type: Balanced
Branch-Predictor:
  Type: "TAGE"
  BTB-Tag-Bits: 11
  Saturating-Count-Bits: 2
  Global-History-Length: 19
  RAS-entries: 8
  Fallback-Static-Predictor: "Always-Taken"
  TAGE-Table-Bits: 12
  Num-TAGE-Tables: 6
  Tag-Length: 8
L1-Data-Memory:
  Interface-Type: Fixed
L1-Instruction-Memory:
  Interface-Type: Flat
LSQ-L1-Interface:
  Access-Latency: 5
  Exclusive: True
  Load-Bandwidth: 128
  Store-Bandwidth: 64
  Permitted-Requests-Per-Cycle: 2
  Permitted-Loads-Per-Cycle: 2
  Permitted-Stores-Per-Cycle: 1
Ports:
  0:
    Portname: FLA
    Instruction-Group-Support:
    - FP
    - SVE
  1:
    Portname: PR
    Instruction-Group-Support:
    - PREDICATE
  2:
    Portname: EXA
    Instruction-Group-Support:
    - INT_SIMPLE
    - INT_MUL
    - STORE_DATA
  3:
    Portname: FLB
    Instruction-Group-Support:
    - FP_SIMPLE
    - FP_MUL
    - SVE_SIMPLE
    - SVE_MUL
  4:
    Portname: EXB
    Instruction-Group-Support:
    - INT_SIMPLE
    - INT_DIV_OR_SQRT
  5:
    Portname: EAGA
    Instruction-Support: 
    - LOAD
    - STORE_ADDRESS
    - INT_SIMPLE_ARTH_NOSHIFT
    - INT_SIMPLE_LOGICAL_NOSHIFT
    - INT_SIMPLE_CMP
  6:
    Portname: EAGB
    Instruction-Support:
    - LOAD
    - STORE_ADDRESS
    - INT_SIMPLE_ARTH_NOSHIFT
    - INT_SIMPLE_LOGICAL_NOSHIFT
    - INT_SIMPLE_CMP
  7:
    Portname: BR
    Instruction-Group-Support:
    - BRANCH
  8:
    Portname: SME
    Instruction-Group-Support:
    - SME
Reservation-Stations:
  0:
    Size: 20
    Dispatch-Rate: 2
    Ports:
    - FLA
    - PR
    - EXA
  1:
    Size: 20
    Dispatch-Rate: 2
    Ports:
    - FLB
    - EXB
  2:
    Size: 10
    Dispatch-Rate: 1
    Ports:
    - EAGA
  3:
    Size: 10
    Dispatch-Rate: 1
    Ports:
    - EAGB
  4:
    Size: 19
    Dispatch-Rate: 1
    Ports:
    - BR
  5:
    Size: 20
    Dispatch-Rate: 1
    Ports:
    - SME
Execution-Units:
  0:
    Pipelined: True
    Blocking-Groups:
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  1:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  2:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  3:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  4:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  5:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  6:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  7:
    Pipelined: True
    Blocking-Groups: 
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
  8:
    Pipelined: True
    Blocking-Groups:
    - INT_DIV_OR_SQRT
    - FP_DIV_OR_SQRT
    - SVE_DIV_OR_SQRT
Latencies:
  0:
    Instruction-Groups: 
    - INT
    Execution-Latency: 2
    Execution-Throughput: 2
  1:
    Instruction-Groups: 
    - INT_SIMPLE_ARTH_NOSHIFT
    - INT_SIMPLE_LOGICAL_NOSHIFT
    - INT_SIMPLE_CVT
    Execution-Latency: 1
    Execution-Throughput: 1
  2:
    Instruction-Groups: 
    - INT_MUL
    Execution-Latency: 5
    Execution-Throughput: 1
  3:
    Instruction-Groups: 
    - INT_DIV_OR_SQRT
    Execution-Latency: 41
    Execution-Throughput: 41
  4:
    Instruction-Groups: 
    - SCALAR_SIMPLE
    - VECTOR_SIMPLE_LOGICAL
    - SVE_SIMPLE_LOGICAL
    - SME_SIMPLE_LOGICAL
    - VECTOR_SIMPLE_CMP
    - SVE_SIMPLE_CMP
    - SME_SIMPLE_CMP
    Execution-Latency: 4
    Execution-Throughput: 1
  5:
    Instruction-Groups: 
    - FP_DIV_OR_SQRT
    Execution-Latency: 29
    Execution-Throughput: 29
  6:
    Instruction-Groups:
    - SCALAR_SIMPLE_CVT
    - VECTOR_SIMPLE
    - SVE_SIMPLE
    - SME_SIMPLE
    - FP_MUL
    - SVE_MUL
    - SME_MUL
    Execution-Latency: 9
    Execution-Throughput: 1
  7:
    Instruction-Groups: 
    - SVE_DIV_OR_SQRT
    - SME_DIV_OR_SQRT
    Execution-Latency: 98
    Execution-Throughput: 98
  8:
    Instruction-Groups: 
    - PREDICATE
    Execution-Latency: 3
    Execution-Throughput: 1
  9:
    Instruction-Groups: 
    - LOAD_SCALAR
    - LOAD_VECTOR
    - STORE_ADDRESS_SCALAR
    - STORE_ADDRESS_VECTOR
    Execution-Latency: 3
    Execution-Throughput: 1
  10:
    Instruction-Groups: 
    - LOAD_SVE
    - LOAD_SME
    - STORE_ADDRESS_SVE
    - STORE_ADDRESS_SME
    Execution-Latency: 6
    Execution-Throughput: 1
# Indexed FMLA instructions split into 2 dependent µops. Latency increased to 15 to mimic such behaviour
# NOTE: Any changes to the capstone opcode list could invalidate the mapping between ARM instructions and the values below
  11:
    Instruction-Opcodes:
    - 1922
    - 1924
    - 1926
    - 2359
    - 2360
    - 2361
    - 2364
    - 2365
    - 2368
    - 2369
    - 2371
    - 2390
    - 2391
    - 2392
    - 2395
    - 2396
    - 2399
    - 2400
    - 2402
    - 2445
    - 2446
    - 2447
    - 2450
    - 2451
    - 2454
    - 2455
    - 2457
    - 2470
    - 2471
    - 2472
    - 2475
    - 2476
    - 2479
    - 2480
    - 2482
    - 3627
    - 3629
    - 3631
    - 3633
    - 3644
    - 3646
    - 3648
    - 3650
    - 3709
    - 3711
    - 3713
    - 3715
    - 4306
    - 4308
    - 4310
    - 4312
    - 4326
    - 4328
    - 4330
    - 4332
    - 4372
    - 4374
    - 4376
    - 4378
    - 4468
    - 4469
    - 4470
    - 4472
    - 4474
    - 4476
    - 4493
    - 4494
    - 4495
    - 4497
    - 4499
    - 4501
    - 4511
    - 4513
    - 4515
    - 4517
    - 4519
    - 4521
    - 4534
    - 4535
    - 4536
    - 4538
    - 4540
    - 4542
    - 4594
    - 4595
    - 4599
    - 4601
    - 4603
    - 4605
    - 4613
    - 4614
    - 4618
    - 4620
    - 4622
    - 4624
    - 4633
    - 4635
    - 4637
    - 4639
    - 4641
    - 4643
    - 5760
    - 5762
    - 5764
    - 5766
    - 5780
    - 5782
    - 5784
    - 5786
    - 5824
    - 5826
    - 5828
    - 5830
    Execution-Latency: 15
    Execution-Throughput: 1
# CPU-Info mainly used to generate a replica of the special (or system) file directory 
# structure
CPU-Info:
  # Set Generate-Special-Dir to True to generate the special files directory, or to False to not.
  # (Not generating the special files directory may require the user to copy over files manually)
  Generate-Special-Dir: True
  # Core-Count MUST be 1 as multi-core is not supported at this time. (A64FX true value is 48)
  Core-Count: 1
  # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)
  Socket-Count: 1
  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (A64FX true value is 1)
  SMT: 1
  # Below are the values needed to generate /proc/cpuinfo
  BogoMIPS: 200.00
  Features: fp asimd evtstrm sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm fcma dcpop sve
  CPU-Implementer: "0x46"
  CPU-Architecture: 8
  CPU-Variant: "0x1"
  CPU-Part: "0x001"
  CPU-Revision: 0
  # Package-Count is used to generate 
  # /sys/devices/system/cpu/cpu{0..Core-Count}/topology/{physical_package_id, core_id}
  Package-Count: 1