refs.bib

@misc{xilinxsynth,
  title = {{Vivado Design Suite User Guide: Synthesis}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf}}
}

@misc{xilinxmem,
  title = {{7 Series FPGAs Memory Resources: User Guide}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf}}
}

@misc{xilinxdsp,
  title = {{7 Series DSP48E1 Slice: User Guide}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf}}
}

@misc{xilinxclb,
  title = {{7 Series FPGAs Configurable Logic Block: User Guide}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf}}
}
  
@misc{vivadofmax,
  title = {{AR\# 57304
Vivado Timing - Where can I find the Fmax of a clock signal in the timing report?}},
  howpublished = {\url{https://www.xilinx.com/support/answers/57304.html}}
}

@misc{xilinxsimtut,
  title = {{Vivado Design Suite Tutorial: Logic Simulation}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug937-vivado-design-suite-simulation-tutorial.pdf}}
}

@misc{ambaaxispec,
  title = {{AMBA AXI and ACE Protocol Specification}},
  howpublished = {\url{http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf}}
}

@misc{xilinxaxiref,
  title = {{Xilinx AXI reference Guide}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf}}
}

@misc{xilinxpacktut,
  title = {{Vivado Design Suite Tutorial: Creating and Packaging Custom IP}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug1119-vivado-creating-packaging-ip-tutorial.pdf}}
}

@misc{xilinxvip,
  title = {{AXI Verification IP v1.1: LogiCORE IP Product Guide}},
  howpublished = {\url{https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_1/pg267-axi-vip.pdf}}
}