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VHDL-LS misses length comparision #189

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ungultig1 opened this issue Aug 21, 2023 · 1 comment

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ungultig1 commented Aug 21, 2023

Hello,

VHDL_LS won’t detect length mismatch on comparing two registers e.g.:
slv_output(13 downto 0) <= slv_result(11 downto 0)

Is there any settings/flags I’ve missed, which activates this error-check also?
Am I able to set any flags for VHDL-LS compiler? Where?

thx. greetings.

Contributor

Rutherther commented Aug 21, 2023

I think this has not been implemented so far see #175.

Schottkyc137 added the enhancement label

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