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aggregate as target does not flag when the same elements are assigned #198

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luscheller opened this issue Sep 11, 2023 · 0 comments
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VHDL Relates to the language front-end for VHDL

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@luscheller
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luscheller commented Sep 11, 2023

The following form of aggregate

(b, b) <= a

is illegal but not flagged by the language server. This should be pretty easy to detect.

Minimal reproducible example:

entity test is
end entity test;

architecture rtl of test is
    signal a: bit_vector(1 downto 0);
    signal b: bit;
begin
    (b, b) <= a;
end architecture;

LRM 10.5.2.1:

It is an error if a given signal or any subelement [of the assignment statement] is identified as a target by more than one element association in [...] an aggregate

@luscheller luscheller changed the title aggregate does not flag for duplicate declarations aggregate as target does not flag when the same elements are assigned Sep 11, 2023
@Schottkyc137 Schottkyc137 added the VHDL Relates to the language front-end for VHDL label May 9, 2024
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