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Missing syntactical elements for VHDL 2008 #225

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11 tasks
Schottkyc137 opened this issue Nov 18, 2023 · 3 comments
Open
11 tasks

Missing syntactical elements for VHDL 2008 #225

Schottkyc137 opened this issue Nov 18, 2023 · 3 comments
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good first issue Good for newcomers VHDL Relates to the language front-end for VHDL

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@Schottkyc137
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The following is a list of elements that are currently not syntactically analyzed. Mostly this is because these elements are rarely used. However, for full compliance with the standard, these should be analyzed eventually.
Some of these can also be a starting point for new developers as these features (e.g., groups) are usually small and self-contained.
Below are also minimal reproducible examples that do not parse as of today.

This is also a good place to request prioritization on a feature if this feature is needed in a codebase.

  • Package declaration inside a declarative part
    entity ent is
    end entity;
    
    architecture arch of ent is
      package my_pkg is
          -- ...
       end package;
    begin
    end arch;
  • Package body inside a declarative part
    entity ent is
    end entity;
    
    architecture arch of ent is
      package my_pkg is
          -- ...
       end my_pkg;
      package body my_pkg is
          -- ...
       end package body;
    begin
    end arch;
  • Disconnect Specification
    disconnect sig after 100 ns;
  • Missing keywords and context where they are used
    • Sequence
    • Property
  • Group declaration
    group my_group : template_name ( A, B ) ;
  • Group template declaration
    group template_name is ( sequence, function ) ;
  • Concurrent select guarded and force assignment
    with a select b <= force c when d, e when f;
    with a select b <= guarded c when d, e when f;
  • Question mark after select
    with a select? b <= c when d, e when f;
  • Release assignment
    a <= release out;
@Schottkyc137 Schottkyc137 added the good first issue Good for newcomers label Mar 6, 2024
@Schottkyc137 Schottkyc137 added the VHDL Relates to the language front-end for VHDL label May 11, 2024
@Schottkyc137 Schottkyc137 changed the title Missing syntactical elements Missing syntactical elements for VHDL 2008 May 11, 2024
@Chris44442
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Hi, I haven't worked with the code base before. I have tried fixing the first of your issues here

I didn't understand what to do in some parts, e.g. in the analyze_declaration function or the HasEntityId impl. I have marked it with TODO. Either way your example code parses now and the package is registered as a LRM 4.7 Package declaration, instead of a LRM 4.9 Package instatiation declaration.

Should I make a PR?

@Schottkyc137
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Hi, I haven't worked with the code base before. I have tried fixing the first of your issues here

I didn't understand what to do in some parts, e.g. in the analyze_declaration function or the HasEntityId impl. I have marked it with TODO. Either way your example code parses now and the package is registered as a LRM 4.7 Package declaration, instead of a LRM 4.9 Package instatiation declaration.

Should I make a PR?

Hi,
first of all thanks a lot for your interest in contributing!
What I have seen looks good so far. I think, that you should indeed open a Draft PR and then I can comment on the bits and pieces that are still unclear.

@Chris44442
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Done.

I will try to add your second task (the package body) too, since I think it should be more or less a similar approach.

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Labels
good first issue Good for newcomers VHDL Relates to the language front-end for VHDL
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