Support for VHDL-2019

[SethGower]

I realize it's fairly new, but having some support for VHDL-2019 eventually would be great. Specifically for the new interface/view mechanic.

Even if to start it doesn't do full analysis, just doesn't complain when you use the view keywords, however not sure if having "partial support" would be doable.

[nselvara]

As an additional commentary, I also link the issue ghdl/ghdl#1958 that's over there at GHDL. It lists all of the LRMs basically which we could also adapt. I just steal it. 😁 I guess they would be okay with that. 😄

@SethGower, if you want, you can also add this list to your first message and I could delete it afterwards.

• LCS-2016-001 "Partially Connected Vectors on Port Map"
• LCS-2016-002 "Allow access and protected type parameters on function interfaces":
• LCS-2016-004 "Allow Protected Type Method Parameters to be Access Types, Protected Types (functions), and File Types":
• LCS-2016-006a "File IO / Textio updates"
• LCS-2016-006c "File IO / Directory I/O"
• LCS-2016-006e "Allow access to system environment variables (baseline)"
• LCS-2016-006f "Expose standard conditional analysis identifiers"
• LCS-2016-007 "Sequential Declaration Regions"
• LCS-2016-011 "Date/Time functions"
• LCS-2016-012 "'IMAGE and TO_STRING for composite types"
• LCS-2016-014 "Composites of Protected Types"
• LCS-2016-014a "Pointers to Composites of Protected Types":
• LCS-2016-015 "Report Calling Path"
• LCS-2016-015a "ReportCallingPath - Current File and Line by function"
• LCS-2016-016 "Anonymous Types"
• LCS-2016-018 "Attributes for Enumerated Types"
• LCS-2016-018a "New attributes - 'index"
• LCS-2016-018d "New attributes - 'designated_type"
• LCS-2016-019 "Inferring Constraints from Initial Values for Signals and Variables"
• LCS-2016-023 "Relax Library Requirement on Configurations"
• LCS-2016-026c "LongIntegers"
• LCS-2016-030 "Garbage Collection"
• LCS-2016-032 "PATH_NAME and Shared Variables and Subprograms"
• LCS-2016-033 "Composition with Protected Types"
• LCS-2016-034 "Protected Types with Generic Clause"
• LCS-2016-036a "Allow for conditional expressions in a declaration (baseline)"
• LCS-2016-041 "Record Introspection / Type Reflection"
• LCS-2016-043 "Attributes for PSL"
• LCS-2016-045a "Interface - defines new mode view construct for composite interface objects"
• LCS-2016-045c "Interface - 'CONVERSE for a mode view"
• LCS-2016-047 "Protected Type: Shared Variables On Entity Interface"
• LCS-2016-049 "Map Generics On Subprogram Call"
• LCS-2016-050 "API for Assert"
• LCS-2016-055a "Syntax regularization - component declarations"
• LCS-2016-059 "Array Type Generics"
• LCS-2016-059a "Allow ordering on any scalar array - related to Array Type Generics"
• LCS-2016-061 "Conditional compilation"
• LCS-2016-071a "Extra optional semicolon at the end of interface_list"
• LCS-2016-072b "Function Knows Return Vector Size"
• LCS-2016-075 "Closely related record types"
• LCS-2016-082 "Syntax regularization: empty records"
• LCS-2016-086 "All Interface Lists Can Be Ordered"
• LCS-2016-094a "Conditional Return Statement"
• LCS-2016-099 "Extended Ranges"

[Schottkyc137]

Closing this as VHDL2019 will be tracked in #287. Thanks for opening this issue!