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[Bug] Packages can't explicitly reference themselves #304

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domWalters opened this issue May 14, 2024 · 1 comment
Open

[Bug] Packages can't explicitly reference themselves #304

domWalters opened this issue May 14, 2024 · 1 comment
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@domWalters
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I am using a public library that has code that can be reduced to this:

package test is

    type enum_1_t is (A_e);
    subtype enum_2_1 is test.enum_1_t;

end package;

This package self reference isn't necessary, but this compiles in Vivado (synthesis and simulation) as well as Modelsim and Riviera, which suggests to me that it's valid VHDL (although I haven't looked in the standard).

VHDL LS provides the following error on the subtype declaration line:

No declaration of enum_1_t within package test

@Schottkyc137
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Related to #249

@Schottkyc137 Schottkyc137 added the bug Something isn't working label May 14, 2024
@Schottkyc137 Schottkyc137 self-assigned this Jul 30, 2024
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