Unreachable code panic when instantiating a component with a generic type

[maltaisn]

The following file:

library ieee;
use ieee.std_logic_1164.all;

entity Foo is
   port (
      clk : in std_logic);
end entity;

architecture Behavioral of Foo is

component Bar
   generic (
      type DATA_TYPE);
   port (
      clk : in std_logic);
end component;

begin

Inst_Bar : Bar
   generic map (
      DATA_TYPE => std_logic)
   port map (
      clk => clk);

end architecture;

Causes a panic:

thread '<unnamed>' panicked at vhdl_lang\src\named_entity\formal_region.rs:101:17:
internal error: entered unreachable code

I'm using v0.83.0.

[jobtijhuis]

I was just about to report this problem, as I ran into it as well.

[maltaisn]

I looked at the code and using subprograms or types in generic associations is simply not implemented. In fact generic associations are treated exactly like port associations at the moment.

On my side I just patched it by adding this line:

        AnyEntKind::Type(_) => TypeEnt::from_any(self.ent).unwrap(),

right after:

rust_hdl/vhdl_lang/src/named_entity/formal_region.rs

Line 99 in 5cf0e4c

AnyEntKind::InterfaceFile(file_type) => *file_type,

Which is definitely wrong but at least there's no panic.

[Schottkyc137]

I just want to say that I'm on it, but I have decided against a quick fix because there currently is a lot of duplicate logic when analyzing interface lists (for example, the capabilities missing for entities is implemented for generic packages and generic subprograms) so I want to simplify the code a bit before rolling out the fix.