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Is your feature request related to a problem? Please describe.
Currently all python int types are converted to signed [31:0] in Verilog. That causes problems when int is larger than what can be represented in 4 bytes.
Describe the solution you'd like
For inputs and outputs:
Add a bytes-needed member to Var class, which is the max of all previous bytes-needed for inputs and outputs.
For variables local to a function, options are:
Add a parameter to verilogify that sets the integer size for local variables of a function.
Use inspect.getgeneratorlocals(generator)
Option 2 should generate more space-efficient hardware.
The text was updated successfully, but these errors were encountered:
Is your feature request related to a problem? Please describe.
Currently all python
int
types are converted tosigned [31:0]
in Verilog. That causes problems when int is larger than what can be represented in 4 bytes.Describe the solution you'd like
For inputs and outputs:
Add a bytes-needed member to
Var
class, which is the max of all previous bytes-needed for inputs and outputs.For variables local to a function, options are:
verilogify
that sets the integer size for local variables of a function.inspect.getgeneratorlocals(generator)
Option 2 should generate more space-efficient hardware.
The text was updated successfully, but these errors were encountered: