Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Dynamic Integer Sizes #123

Open
WorldofKerry opened this issue Sep 10, 2023 · 0 comments
Open

Dynamic Integer Sizes #123

WorldofKerry opened this issue Sep 10, 2023 · 0 comments
Labels
good first issue Good for newcomers

Comments

@WorldofKerry
Copy link
Owner

WorldofKerry commented Sep 10, 2023

Is your feature request related to a problem? Please describe.
Currently all python int types are converted to signed [31:0] in Verilog. That causes problems when int is larger than what can be represented in 4 bytes.

Describe the solution you'd like
For inputs and outputs:
Add a bytes-needed member to Var class, which is the max of all previous bytes-needed for inputs and outputs.

For variables local to a function, options are:

  1. Add a parameter to verilogify that sets the integer size for local variables of a function.
  2. Use inspect.getgeneratorlocals(generator)

Option 2 should generate more space-efficient hardware.

@WorldofKerry WorldofKerry added the enhancement New feature or request label Sep 10, 2023
@WorldofKerry WorldofKerry added good first issue Good for newcomers and removed enhancement New feature or request labels Oct 20, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
good first issue Good for newcomers
Projects
Status: Backlog
Development

No branches or pull requests

1 participant