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We have found that some of documented (1) intrinsics are not supported. Please find the reproducer code below. Enabling CASE1 or CASE2 results in an error. Is the documentation wrong or is it a compiler problem?
#include<riscv_vector.h>
#defineCASE10
#defineCASE20intmain()
{
#if CASE1
// does not work// snippet.cpp:16:26: error: 'vlmul_trunc_v_i64m2_i64m1' was not declared in this scope; did you mean 'vget_v_i64m2_i64m1'?// 12 | vint64m1_t dst = vlmul_trunc_v_i64m2_i64m1(src);// | ^~~~~~~~~~~~~~~~~~~~~~~~~// | vget_v_i64m2_i64m1
{
vint64m2_t src;
vint64m1_t dst = vlmul_trunc_v_i64m2_i64m1(src);
}
#endif
#if CASE2
// works
{
int8_t data[1000] = {0};
vuint8m1_t bindex;
vint8m1_t dst = vloxei8_v_i8m1 (data, bindex, 8);
}
// does not work// snippet.cpp:37:25: error: 'vloxei32_v_i8m1' was not declared in this scope; did you mean 'vloxei32_v_i32m1'?// 18 | vint8m1_t dst = vloxei32_v_i8m1 (data, bindex, 8);// | ^~~~~~~~~~~~~~~// | vloxei32_v_i32m1
{
int8_t data[1000] = {0};
vuint32m4_t bindex;
vint8m1_t dst = vloxei32_v_i8m1 (data, bindex, 8);
}
#endifreturn0;
}
We have found that some of documented (1) intrinsics are not supported. Please find the reproducer code below. Enabling CASE1 or CASE2 results in an error. Is the documentation wrong or is it a compiler problem?
Compilation command:
Compiler version:
RVV intrinscs documentation found here: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource/1836682/1638774209491/Xuantie+900+Series+RVV-0.7.1+Intrinsic+Manual.pdf
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