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CHaiDNN build error #179

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btwbtw01 opened this issue Aug 5, 2021 · 0 comments
Open

CHaiDNN build error #179

btwbtw01 opened this issue Aug 5, 2021 · 0 comments

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@btwbtw01
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btwbtw01 commented Aug 5, 2021

Hi everyone,
I try to build the hardware from makefile. I follow instructions from https://github.com/Xilinx/CHaiDNN. However I got this error.
===>The following messages were generated while processing /home/bryan/Documents/CHaiDNN-master/design/build/_sds/p0/vivado/prj/prj.runs/impl_1 :
ERROR: [VPL 17-179] Fork failed: Cannot allocate memory
ERROR: [VPL 17-179] Fork failed: Cannot allocate memory
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, Design Initialization ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx/SDx/2018.2/bin/vpl --iprepo /home/bryan/Documents/CHaiDNN-master/design/build/_sds/iprepo/repo --iprepo /opt/Xilinx/SDx/2018.2/data/ip/xilinx --platform /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm --temp_dir /home/bryan/Documents/CHaiDNN-master/design/build/_sds/p0 --output_dir /home/bryan/Documents/CHaiDNN-master/design/build/_sds/p0/vpl --input_file /home/bryan/Documents/CHaiDNN-master/design/build/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels XiConvolutionTop:PoolTop:XiDeconvTop:adapter --webtalk_flag SDSoC --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" --xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1" --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={/home/bryan/Documents/CHaiDNN-master/design/build/../conv/scripts/mcps.tcl}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={/home/bryan/Documents/CHaiDNN-master/design/build/../conv/scripts/mcps.tcl}" --xp "param:compiler.deleteDefaultReportConfigs=false" '
sds++ log file saved as /home/bryan/Documents/CHaiDNN-master/design/build/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

Makefile:147: recipe for target 'libxlnxdnn.so' failed
make: *** [libxlnxdnn.so] Error 1

I'm using VMware with ubuntu 16.04.3 and SDx 2018.2, and the memory is 5.7G.

By the way, I skip the first step and use zcu102 default when I face the error above. When I generate custom platform and run makefile, I face another error.
INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0
INFO: [DMAnalysis 83-4446] Creating data motion network hardware for partition 0
WARNING: [DMAnalysis 83-10051] Invalid clock id 3 for platform zcu102
WARNING: [DMAnalysis 83-10051] Invalid clock id 3 for platform zcu102
ERROR: [DMAnalysis 83-13491] Invalid clock id '3' for component 'PoolTop'. Requested clock period = -1, minimum supported period = 5
ERROR: [DMAnalysis 83-4403] Failed to allocate comp PoolTop
ERROR: [DMAnalysis 83-4447] Failed creating data motion network hardware!
/opt/Xilinx/SDx/2018.2/bin/XidanePass: 1: /opt/Xilinx/SDx/2018.2/bin/XidanePass: gawk: not found
Data motion generation exited with return code 1

  • errors detected
    sds++ log file saved as /home/bryan/Documents/CHaiDNN-master/design/build/_sds/reports/sds.log
    ERROR: [SdsCompiler 83-5004] Build failed

Makefile:148: recipe for target 'libxlnxdnn.so' failed
make: *** [libxlnxdnn.so] Error 1

Can I skip the first step? Please help me solve these errors. Thanks a lot.

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