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version.txt
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# Copyright 2020 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
//////////////// VERSION 0.3.5 ////////////////
NEW FEATURES:
- /
UPDATES:
- /
BUG FIXES:
- Refactor py_initialize to avoid starting python interpreter if not needed
UNFIXED ISSUES:
- /
//////////////// VERSION 0.3.4 ////////////////
NEW FEATURES:
- Add DPUCVDX8G-DWC target
- Add u50-lv and u55c targets
UPDATES:
- /
BUG FIXES:
- Eagerly load runtime modules to avoid Tensorflow being imported if not needed
(Fix for TVM: https://github.com/apache/tvm/issues/10696#issuecomment-1081764081)
UNFIXED ISSUES:
- /
//////////////// VERSION 0.3.3 ////////////////
NEW FEATURES:
- Add dropout layer support by skipping it if found
- Offload non-zero pad to CPU
UPDATES:
- /
BUG FIXES:
- Fix frontend Schedule object not supporting item deletion
- Fix Conv2DTranspose shape
- Use correct VCK5000 arch file
UNFIXED ISSUES:
- /
//////////////// VERSION 0.3.2 ////////////////
NEW FEATURES:
- /
UPDATES:
- Add default shift bias and shift cut values in decent quantize config
- Add Relay PReLU to XLayer and update PReLU to accept a vector alpha
BUG FIXES:
- Fix partitioning bug for BiasAdd followed by ReLU
- Fix Relay to XLayer Reshape op
- Fix Relay to XLayer strided slice for end > max
- Fix for hidden outputs not being recognized; Added exxplicit identity
output in TF generation for hidden outputs
UNFIXED ISSUES:
- /
//////////////// VERSION 0.3.1 ////////////////
NEW FEATURES:
- Add Relay resize2d op translation to XLayer
UPDATES:
- Decouple external quantizer flow for DPUCAHX8H/L and DPUCVDX8G/H
BUG FIXES:
- Put tighter previous layer constraints on DPU ReLU support checks
UNFIXED ISSUES:
- /
//////////////// VERSION 0.3.0 ////////////////
NEW FEATURES:
- Add DPUCADF8G (U200/U250) target
- Add DPUCVDX8H (VCK5000) target
- Add DPUCVDX8G (VCK190) target
- Add DPUCAHX8L (U50/U280) target
- Add DPUCZDX8G-kv260 (Kria SOM) target
UPDATES:
- Add support for auto pad attributes in ONNX pooling translation to XLayer
- Compile with -O3 optimization level
BUG FIXES:
- Fix ONNX Conv2D auto pad attribute translation to XLayer
- Fix Relay strided_slice op translation to XLayer
- Aanitize XLayer names to avoid unsupported TF naming characters
- Use RTLD_DEEPBIND dlopen for Tensorflow to avoid error due to different protobuf versions in AKS flow
UNFIXED ISSUES:
- /
//////////////// VERSION 0.2.1 ////////////////
NEW FEATURES:
- /
UPDATES:
- Add support for padding value argument instead of attribute in latest TVM Relay padding op
BUG FIXES:
- Fix DNNC output parsing issue if non-alphabetic and/or non-numeric characters exist in
the output names
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.2.0 ////////////////
NEW FEATURES:
- Create DPUCZDX8G (zcu104, zcu102, SOM and Ultra96) VART flow
UPDATES:
- Update TVM example scripts
BUG FIXES:
- Fix LeakyRelu for XCompiler backend (for DPUCAHX8H target)
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.1.7 ////////////////
NEW FEATURES:
- Run quantization in batches of 32, allowing larger calibration datasets
UPDATES:
- Update TVM example scripts to latest partitioning and TVM runtime API's
- Make RuntimeModule load from file function static
BUG FIXES:
- Fix for dilated conv2d
- Fix for unsupported op inside resnet/inception-like block
- Fix C++ ONNX IO tests
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.1.6 ////////////////
NEW FEATURES:
- Add DPUCZDX8G SOM target
- Enable DPUCAHX8H (U50, U280) targets
- Try importing DPU targets in TargetRegistry if not found
BUG FIXES:
- Fix for TVM RPC flow
- Fix for ONNX Runtime edge flow
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.1.5 ////////////////
NEW FEATURES:
- Add TVM Relay tile, full ops to XLayer translation
- Add TVM Relay image.resize to XLayer translation and to Upsampling2D if applicable
- Add pattern annotator for discovering and annotating patterns, e.g. mul + max = leaky relu
- Add Decent quantizer simulation support on x86
- Add full TVM ResNet 18 example
BUG FIXES:
- Fix bug in reading PX_VERBOSE environment veriable
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.1.4 ////////////////
NEW FEATURES:
- Extend model coverage to SSD type networks
- Add external quantizer supporyt (Brevitas)
- Add support for ONNX Runtime DPUCZDX8G (edge) flow through automatic serialization
- Refactor Relay frontend and improve coverage
- Support conv2d OHWI kernel layout
- Reduce h5py dependency from 2.10.0 to 2.8.0
- Use dnnc-dpuv2 compiler for Vitis AI 1.3 release
BUG FIXES:
- Fix TF layer naming bug that could cause operations to be missed
- Fix bug in XBuffer move and copy constructors
- Fix bug in XBuffer stride inferral for buffers with dim 0 size > 1
- Add correct in/out dimensions Vitis AI runtime batch tensors
UNFIXED ISSUES:
- Importing tvm before pyxir results in segfault for DPUCADX8G env due to
protobuf mismatch between DPUCADX8G tools and tensorflow
//////////////// VERSION 0.1.3 ////////////////
NEW FEATURES:
- Add serialization for XGraph and RuntimeModule
BUG FIXES:
- Fix Conv2DTranspose compilation for DPUCADX8G
UNFIXED ISSUES:
- /
//////////////// VERSION 0.1.2 ////////////////
NEW FEATURES:
- /
BUG FIXES:
- Small fix for Relay batch norm to XGraph translation when no scale or beta found
UNFIXED ISSUES:
- /
//////////////// VERSION 0.1.1 ////////////////
NEW FEATURES:
- Support for edge DPUCZDX8G/DPUv2 in C++ Vitis-AI runtime
- Support for NHWC networks in Vitis-AI runtime
- Enable cross-compilation for all accelerator targets
- Add DPUCZDX8G Ultra96 target
BUG FIXES:
- Keep track of XGraph meta attributes during serialization
UNFIXED ISSUES:
- /
//////////////// VERSION 0.1.0 ////////////////
NEW FEATURES:
- Support for DPUv1 and DPUv2 Vitis-AI accelerator targets
- Experimental ONNXRuntime integration
- Experimental TVM integration
- Tools for generic partitioning, graph optimization and simulation at the IR level
BUG FIXES:
- /
UNFIXED ISSUES:
- /