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I can see the SOLO is added in Vitis_AI_2 model zoo but seems supported only for Versal boards. I am trying to compile it for ZCU104 but couldn't make it yet.
Is it a hardware limitation or just due to a performance issue that SOLO is not provided for Zynq Ultrascale boards?
How to pull specific layers alone onto dpu and compile most for CPU with TVM/pyxir?
Thanks.
The text was updated successfully, but these errors were encountered:
I can see the SOLO is added in Vitis_AI_2 model zoo but seems supported only for Versal boards. I am trying to compile it for ZCU104 but couldn't make it yet.
Thanks.
The text was updated successfully, but these errors were encountered: