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I have a verilog module that have an AXI4 Lite slave interface and interrupt output. I will implement a kernel module for it to handle module's interrupts and reading its registers.
For the AXI part the demo may be helpful, but I could not find an example with interrupt.
Can you prepare a demo project that handles my case?
Thanks.
The text was updated successfully, but these errors were encountered:
Hi,
I have a verilog module that have an AXI4 Lite slave interface and interrupt output. I will implement a kernel module for it to handle module's interrupts and reading its registers.
For the AXI part the demo may be helpful, but I could not find an example with interrupt.
Can you prepare a demo project that handles my case?
Thanks.
The text was updated successfully, but these errors were encountered: