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qflexpress.txt
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################################################################################
##
## Filename: qflexpress.txt
## {{{
## Project: A Set of Wishbone Controlled SPI Flash Controllers
##
## Purpose: Describes the Quad-I/O flash peripheral for AutoFPGA.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2018-2021, Gisselquist Technology, LLC
## {{{
## This file is part of the set of Wishbone controlled SPI flash controllers
## project
##
## The Wishbone SPI flash controller project is free software (firmware):
## you can redistribute it and/or modify it under the terms of the GNU Lesser
## General Public License as published by the Free Software Foundation, either
## version 3 of the License, or (at your option) any later version.
##
## The Wishbone SPI flash controller project is distributed in the hope
## that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
## warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: LGPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/lgpl.html
##
##
################################################################################
##
## }}}
@PREFIX=flash
@DEVID=FLASH
@ACCESS=@$(DEVID)_ACCESS
@$LGFLASHSZ=24
@$NADDR=(1<<(@$LGFLASHSZ-2))
@$NBYTES=(1<<@$LGFLASHSZ)
@NBYTES.FORMAT=0x%08x
@ACCESS= FLASH_ACCESS
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wb
@NDUMMY=6
@RDDELAY=1
@STARTUP_SCRIPT="spansion.hex"
@TOP.PORTLIST=
// Top level Quad-SPI I/O ports
o_qspi_cs_n, o_qspi_sck, io_qspi_dat
@TOP.IODECL=
// Quad SPI flash
output wire o_qspi_cs_n;
output wire o_qspi_sck;
inout wire [3:0] io_qspi_dat;
@TOP.DEFNS=
wire w_qspi_sck, w_qspi_cs_n;
wire [1:0] qspi_bmod;
wire [3:0] qspi_dat;
wire [3:0] i_qspi_dat, i_qspi_pedge, i_qspi_nedge;
@TOP.MAIN=
// Quad SPI flash
w_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod
@TOP.INSERT=
//
//
// Wires for setting up the QSPI flash wishbone peripheral
//
//
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
// 0? Normal serial mode, one bit in one bit out
// 10 Quad SPI mode, going out
// 11 Quad SPI mode coming from the device (read mode)
`ifdef XILINX
xoddr xqspi_sck( s_clk, { 1'b1, !w_qspi_sck }, o_qspi_sck);
xoddr xqspi_csn( s_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
//
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11), { (2){qspi_dat[0]}},
{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
xioddr xqspi_d1( s_clk, (qspi_bmod == 2'b10), { (2){qspi_dat[1]}},
{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
xioddr xqspi_d2( s_clk, (qspi_bmod != 2'b11),
qspi_bmod[1] ? { (2){qspi_dat[2]}} : 2'b11,
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
xioddr xqspi_d3( s_clk, (qspi_bmod != 2'b11),
qspi_bmod[1] ? { (2){qspi_dat[3]}} : 2'b11,
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
assign i_qspi_dat = i_qspi_pedge;
##
##
@XDC.INSERT=
set_property SLEW FAST [get_ports o_qspi_cs_n]
set_property SLEW FAST [get_ports o_qspi_sck]
set_property SLEW FAST [get_ports io_qspi_dat[0]]
set_property SLEW FAST [get_ports io_qspi_dat[1]]
set_property SLEW FAST [get_ports io_qspi_dat[2]]
set_property SLEW FAST [get_ports io_qspi_dat[3]]
##
##
##
`else
assign io_qspi_dat = (!qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
assign o_qspi_cs_n = w_qspi_cs_n;
`endif // XILINX
@MAIN.PORTLIST=
// The Universal QSPI Flash
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod
@MAIN.IODECL=
// The Universal QSPI flash
output wire o_qspi_cs_n, o_qspi_sck;
output wire [3:0] o_qspi_dat;
input wire [3:0] i_qspi_dat;
output wire [1:0] o_qspi_mod;
@MAIN.DEFNS=
// Definitions for the @$(PREFIX) debug port
wire @$(PREFIX)_dbg_trigger;
wire [31:0] @$(PREFIX)_debug;
@MAIN.INSERT=
qflexpress #(.LGFLASHSZ(@$LGFLASHSZ), .OPT_CLKDIV(1),
.OPT_ENDIANSWAP(0),
.NDUMMY(@$(NDUMMY)), .RDDELAY(@$(RDDELAY)),
.OPT_STARTUP_FILE(@$(STARTUP_SCRIPT)),
`ifdef FLASHCFG_ACCESS
.OPT_CFG(1'b1)
`else
.OPT_CFG(1'b0)
`endif
)
@$(PREFIX)i(i_clk, i_reset,
(wb_cyc), (wb_stb)&&(@$(PREFIX)_sel),
(wb_stb)&&(flashcfg_sel), wb_we,
wb_addr[(@$LGFLASHSZ-3):0], wb_data,
@$(PREFIX)_ack, @$(PREFIX)_stall, @$(PREFIX)_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_dbg_trigger, flash_debug);
@MAIN.ALT=
assign o_qspi_sck = 1'b1;
assign o_qspi_cs_n = 1'b1;
assign o_qspi_mod = 2'b01;
assign o_qspi_dat = 4'b1111;
@MEM.NAME= flash
@MEM.ACCESS = rx
@REGS.N= 1
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
#define @$(DEVID)LGLEN @$LGFLASHSZ
//
#define FLASH_RDDELAY @$(RDDELAY)
#define FLASH_NDUMMY @$(NDUMMY)
//
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern int _@$(PREFIX)[1];
@LD.PERM= rx
@LD.NAME= @$(PREFIX)
@SIM.INCLUDE=
#include "flashsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
FLASHSIM *m_@$(MEM.NAME);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(MEM.NAME) = new FLASHSIM(FLASHLGLEN, false, @$RDDELAY, @$NDUMMY);
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_qspi_dat = m_@$(MEM.NAME)->simtick(
m_core->o_qspi_cs_n,
m_core->o_qspi_sck,
m_core->o_qspi_dat,
m_core->o_qspi_mod);
#endif // @$(ACCESS)
@SIM.LOAD=
#ifdef @$(ACCESS)
m_@$(MEM.NAME)->load(start, &buf[offset], wlen);
#endif // @$(ACCESS)
##
##
##
##
## Now the control interface
@PREFIX=flashcfg
@NADDR=1
@DEVID=FLASHCFG
@ACCESS=@$(DEVID)_ACCESS
@DEPENDS= FLASH_ACCESS
## Although this is really a SLAVE.TYPE=SINGLE interface, it receives its
## acknowledgements from the flash above. SLAVE.TYPE=SINGLE will create
## acknowledgements in the interconnect, resulting in bus errors. As a result,
## this must be a SLAVE.TYPE=OTHER
##
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb
@MAIN.INSERT=
// The Flash control interface result comes back together with the
// flash interface itself. Hence, we always return zero here.
assign @$(PREFIX)_ack = 1'b0;
assign @$(PREFIX)_stall = 1'b0;
assign @$(PREFIX)_data = flash_data;
@REGS.NOTE= // FLASH erase/program configuration registers
@REGS.N= 1
@REGS.0= 0 R_@$(DEVID) @$(DEVID) QSPIC
@REGDEFS.H.INSERT=
// Flash control constants
#define QSPI_FLASH // This core and hardware support a Quad SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
@BDEF.IONAME= _@$(PREFIX)
@BDEF.OSDEF= _BOARD_HAS_@$(DEVID)
@BDEF.IOTYPE=unsigned
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) * const @$(BDEF.IONAME) = ((@$BDEF.IOTYPE *)(@$[0x%08x](REGBASE)));
##
@RTL.MAKE.GROUP= FLASH
@RTL.MAKE.FILES= qflexpress.v