Skip to content

Commit 90a2541

Browse files
liguangblueswirl
liguang
authored andcommitted
target-i386: fix over 80 chars warnings
Signed-off-by: liguang <[email protected]> Reviewed-by: Andreas Färber <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Blue Swirl <[email protected]>
1 parent 0bc60a8 commit 90a2541

File tree

3 files changed

+39
-22
lines changed

3 files changed

+39
-22
lines changed

Diff for: target-i386/misc_helper.c

+26-13
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,8 @@ void helper_cpuid(CPUX86State *env)
122122

123123
cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
124124

125-
cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
125+
cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
126+
&eax, &ebx, &ecx, &edx);
126127
env->regs[R_EAX] = eax;
127128
env->regs[R_EBX] = ebx;
128129
env->regs[R_ECX] = ecx;
@@ -271,7 +272,8 @@ void helper_wrmsr(CPUX86State *env)
271272

272273
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
273274

274-
val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
275+
val = ((uint32_t)env->regs[R_EAX]) |
276+
((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
275277

276278
switch ((uint32_t)env->regs[R_ECX]) {
277279
case MSR_IA32_SYSENTER_CS:
@@ -350,7 +352,8 @@ void helper_wrmsr(CPUX86State *env)
350352
case MSR_MTRRphysBase(5):
351353
case MSR_MTRRphysBase(6):
352354
case MSR_MTRRphysBase(7):
353-
env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
355+
env->mtrr_var[((uint32_t)env->regs[R_ECX] -
356+
MSR_MTRRphysBase(0)) / 2].base = val;
354357
break;
355358
case MSR_MTRRphysMask(0):
356359
case MSR_MTRRphysMask(1):
@@ -360,14 +363,17 @@ void helper_wrmsr(CPUX86State *env)
360363
case MSR_MTRRphysMask(5):
361364
case MSR_MTRRphysMask(6):
362365
case MSR_MTRRphysMask(7):
363-
env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
366+
env->mtrr_var[((uint32_t)env->regs[R_ECX] -
367+
MSR_MTRRphysMask(0)) / 2].mask = val;
364368
break;
365369
case MSR_MTRRfix64K_00000:
366-
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
370+
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
371+
MSR_MTRRfix64K_00000] = val;
367372
break;
368373
case MSR_MTRRfix16K_80000:
369374
case MSR_MTRRfix16K_A0000:
370-
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
375+
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
376+
MSR_MTRRfix16K_80000 + 1] = val;
371377
break;
372378
case MSR_MTRRfix4K_C0000:
373379
case MSR_MTRRfix4K_C8000:
@@ -377,7 +383,8 @@ void helper_wrmsr(CPUX86State *env)
377383
case MSR_MTRRfix4K_E8000:
378384
case MSR_MTRRfix4K_F0000:
379385
case MSR_MTRRfix4K_F8000:
380-
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
386+
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
387+
MSR_MTRRfix4K_C0000 + 3] = val;
381388
break;
382389
case MSR_MTRRdefType:
383390
env->mtrr_deftype = val;
@@ -399,7 +406,8 @@ void helper_wrmsr(CPUX86State *env)
399406
break;
400407
default:
401408
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
402-
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
409+
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
410+
(4 * env->mcg_cap & 0xff)) {
403411
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
404412
if ((offset & 0x3) != 0
405413
|| (val == 0 || val == ~(uint64_t)0)) {
@@ -480,7 +488,8 @@ void helper_rdmsr(CPUX86State *env)
480488
case MSR_MTRRphysBase(5):
481489
case MSR_MTRRphysBase(6):
482490
case MSR_MTRRphysBase(7):
483-
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
491+
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
492+
MSR_MTRRphysBase(0)) / 2].base;
484493
break;
485494
case MSR_MTRRphysMask(0):
486495
case MSR_MTRRphysMask(1):
@@ -490,14 +499,16 @@ void helper_rdmsr(CPUX86State *env)
490499
case MSR_MTRRphysMask(5):
491500
case MSR_MTRRphysMask(6):
492501
case MSR_MTRRphysMask(7):
493-
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
502+
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
503+
MSR_MTRRphysMask(0)) / 2].mask;
494504
break;
495505
case MSR_MTRRfix64K_00000:
496506
val = env->mtrr_fixed[0];
497507
break;
498508
case MSR_MTRRfix16K_80000:
499509
case MSR_MTRRfix16K_A0000:
500-
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
510+
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
511+
MSR_MTRRfix16K_80000 + 1];
501512
break;
502513
case MSR_MTRRfix4K_C0000:
503514
case MSR_MTRRfix4K_C8000:
@@ -507,7 +518,8 @@ void helper_rdmsr(CPUX86State *env)
507518
case MSR_MTRRfix4K_E8000:
508519
case MSR_MTRRfix4K_F0000:
509520
case MSR_MTRRfix4K_F8000:
510-
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
521+
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
522+
MSR_MTRRfix4K_C0000 + 3];
511523
break;
512524
case MSR_MTRRdefType:
513525
val = env->mtrr_deftype;
@@ -539,7 +551,8 @@ void helper_rdmsr(CPUX86State *env)
539551
break;
540552
default:
541553
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
542-
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
554+
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
555+
(4 * env->mcg_cap & 0xff)) {
543556
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
544557
val = env->mce_banks[offset];
545558
break;

Diff for: target-i386/seg_helper.c

+9-7
Original file line numberDiff line numberDiff line change
@@ -1811,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
18111811
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
18121812
/* to inner privilege */
18131813
get_ss_esp_from_tss(env, &ss, &sp, dpl);
1814-
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
1815-
"\n",
1816-
ss, sp, param_count, env->regs[R_ESP]);
1814+
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1815+
TARGET_FMT_lx "\n", ss, sp, param_count,
1816+
env->regs[R_ESP]);
18171817
if ((ss & 0xfffc) == 0) {
18181818
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
18191819
}
@@ -1847,16 +1847,18 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
18471847
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
18481848
PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
18491849
for (i = param_count - 1; i >= 0; i--) {
1850-
val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
1851-
old_sp_mask));
1850+
val = cpu_ldl_kernel(env, old_ssp +
1851+
((env->regs[R_ESP] + i * 4) &
1852+
old_sp_mask));
18521853
PUSHL(ssp, sp, sp_mask, val);
18531854
}
18541855
} else {
18551856
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
18561857
PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
18571858
for (i = param_count - 1; i >= 0; i--) {
1858-
val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
1859-
old_sp_mask));
1859+
val = cpu_lduw_kernel(env, old_ssp +
1860+
((env->regs[R_ESP] + i * 2) &
1861+
old_sp_mask));
18601862
PUSHW(ssp, sp, sp_mask, val);
18611863
}
18621864
}

Diff for: target-i386/svm_helper.c

+4-2
Original file line numberDiff line numberDiff line change
@@ -658,8 +658,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
658658
R_DS);
659659

660660
env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
661-
env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
662-
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
661+
env->regs[R_ESP] = ldq_phys(env->vm_hsave +
662+
offsetof(struct vmcb, save.rsp));
663+
env->regs[R_EAX] = ldq_phys(env->vm_hsave +
664+
offsetof(struct vmcb, save.rax));
663665

664666
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
665667
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));

0 commit comments

Comments
 (0)