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RTX 5080 lane: needs a smaller pinned artifact; blocked on VRAM (nvfp4 does not reduce size) #28

Description

@alphastorm

Context

Community request (Discord, 2026-08-30). The RTX 5080 is the same Blackwell family as the
qualified RTX 5090 lane (sm_120), so the existing kernel work largely applies — this is not a
new port in the CUDA sense. The blocker is VRAM, not kernels.

The hard wall

The pinned Qwen3.8 27B artifact is 18.2 GB of weights alone (18,210,531,328 bytes) against
the 5080's 16 GB. It cannot load before budgeting a single KV byte — the 24 GB cards only
work via rk2v4-e8 KV quantization on top of weights that already fit.

What would make it possible

  • A smaller pinned artifact — i.e. the nvfp4 swap already on the roadmap as the v0.4-class
    decision
    (~4 bpw ≈ 13.5–14 GB). Even then the context ceiling drops hard (likely ~32–48K,
    not 131K, with aggressive KV compression).
  • Alternatively a smaller model, which changes the product.

Process reality

"Support" in this repository means an exact qualified lane with receipts. That requires real
RTX 5080 hardware in the fleet (currently none) and a qualification campaign like the RTX 4090
MTP3 campaign (v0.3.1 receipts).

Outcome

Track RTX 5080 as a post-nvfp4 candidate lane with a reduced-context profile, gated on:

  • the nvfp4 artifact decision (v0.4-class, forces three-lane requalification — see
    ROADMAP.md → After v0.3.0)
  • a measured reduced-context profile that fits 16 GB (weights + KV + activations)
  • RTX 5080 hardware available for a receipts-bound qualification campaign

Not addable before the artifact decision.

Activity

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