diff --git a/sw/examples/spi_example.py b/sw/examples/spi_example.py
index 37869de..6770abc 100644
--- a/sw/examples/spi_example.py
+++ b/sw/examples/spi_example.py
@@ -21,6 +21,9 @@
 # Set the CS line as an output
 bridge.gpiocfg(CS_PIN, 'output')
 
+# Configure ~1.05MHz clock with CPOL=0,CPHA=0
+bridge.spi_cfg(10500000, 0, 0)
+
 # CS is active low in this case
 bridge.gpio(CS_PIN, 1)
 
diff --git a/sw/silta/stm32f407.py b/sw/silta/stm32f407.py
index 4f44a5f..e62a6b9 100644
--- a/sw/silta/stm32f407.py
+++ b/sw/silta/stm32f407.py
@@ -261,6 +261,32 @@ def spi(self, cspin, wbytes = []):
 
         return rbytes
 
+    def spicfg(self, speed, cpol, cpha):
+        ''' SPI Configuration
+
+            Arguments:
+            speed - SPI Speed in Hz
+                Supported speeds: 42000000, 21000000, 10500000, 5250000, 
+                                    2625000, 1312500, 656250, 328125
+            cpol - Clock polarity
+            cpha - Clock phase
+
+            Return Values:
+            True for success
+            or
+            False for failure
+        '''
+
+        cmd = 'spicfg ' + str(speed) + ' ' + str(int(cpol) & 1) + ' ' + str(int(cpha) & 1)
+        line = self.__send_cmd(cmd)
+        
+        result = line.strip().split(' ')
+
+        if result[0] == 'OK':
+            return True
+        else:
+            return False
+
     # Configure GPIO as input/output/etc
     def gpiocfg(self, name, mode='input', pull=None):
         ''' GPIO Configuration