diff --git a/tests/test_csr_action.py b/tests/test_csr_action.py
index 9927094..5e31baa 100644
--- a/tests/test_csr_action.py
+++ b/tests/test_csr_action.py
@@ -26,7 +26,7 @@ def process():
 
         sim = Simulator(dut)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
@@ -49,7 +49,7 @@ def process():
 
         sim = Simulator(dut)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
@@ -82,7 +82,7 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
@@ -123,7 +123,7 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
@@ -164,7 +164,7 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
diff --git a/tests/test_csr_bus.py b/tests/test_csr_bus.py
index 3039a8a..d45415e 100644
--- a/tests/test_csr_bus.py
+++ b/tests/test_csr_bus.py
@@ -324,7 +324,7 @@ def sim_test():
                 sim = Simulator(dut)
                 sim.add_clock(1e-6)
                 sim.add_testbench(sim_test)
-                with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+                with sim.write_vcd(vcd_file="test.vcd"):
                     sim.run()
 
 
@@ -362,7 +362,7 @@ def sim_test():
                 sim = Simulator(dut)
                 sim.add_clock(1e-6)
                 sim.add_testbench(sim_test)
-                with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+                with sim.write_vcd(vcd_file="test.vcd"):
                     sim.run()
 
 
@@ -463,5 +463,5 @@ def sim_test():
         sim = Simulator(m)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
diff --git a/tests/test_csr_event.py b/tests/test_csr_event.py
index 0edeaab..f24601d 100644
--- a/tests/test_csr_event.py
+++ b/tests/test_csr_event.py
@@ -12,7 +12,7 @@ def simulation_test(dut, process):
     sim = Simulator(dut)
     sim.add_clock(1e-6)
     sim.add_testbench(process)
-    with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+    with sim.write_vcd(vcd_file="test.vcd"):
         sim.run()
 
 
diff --git a/tests/test_csr_reg.py b/tests/test_csr_reg.py
index bc3e1b9..02a04ce 100644
--- a/tests/test_csr_reg.py
+++ b/tests/test_csr_reg.py
@@ -642,7 +642,7 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_sim_single(self):
@@ -681,7 +681,7 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 class _MockRegister(Register, access="rw"):
@@ -1050,5 +1050,5 @@ def process():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(process)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
diff --git a/tests/test_csr_wishbone.py b/tests/test_csr_wishbone.py
index e9f252f..717156e 100644
--- a/tests/test_csr_wishbone.py
+++ b/tests/test_csr_wishbone.py
@@ -151,7 +151,7 @@ def sim_test():
         sim = Simulator(m)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_wide(self):
@@ -230,5 +230,5 @@ def sim_test():
         sim = Simulator(m)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
diff --git a/tests/test_event.py b/tests/test_event.py
index bf4601b..ce90a73 100644
--- a/tests/test_event.py
+++ b/tests/test_event.py
@@ -12,7 +12,7 @@ def simulation_test(dut, process):
     sim = Simulator(dut)
     sim.add_clock(1e-6)
     sim.add_testbench(process)
-    with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+    with sim.write_vcd(vcd_file="test.vcd"):
         sim.run()
 
 
diff --git a/tests/test_gpio.py b/tests/test_gpio.py
index 5a64466..a1ed014 100644
--- a/tests/test_gpio.py
+++ b/tests/test_gpio.py
@@ -330,7 +330,7 @@ def testbench():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(testbench)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_sim_without_input_sync(self):
@@ -349,5 +349,5 @@ def testbench():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(testbench)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
diff --git a/tests/test_wishbone_bus.py b/tests/test_wishbone_bus.py
index 8c8ad5f..9da371e 100644
--- a/tests/test_wishbone_bus.py
+++ b/tests/test_wishbone_bus.py
@@ -283,7 +283,7 @@ def sim_test():
 
         sim = Simulator(dut)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_addr_translate(self):
@@ -394,7 +394,7 @@ def sim_test():
         m.submodules += dut, loop_1, loop_2, loop_3, loop_4
         sim = Simulator(m)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_coarse_granularity(self):
@@ -416,7 +416,7 @@ def sim_test():
 
         sim = Simulator(dut)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
 
@@ -534,7 +534,7 @@ def sim_test():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_lock(self):
@@ -587,7 +587,7 @@ def sim_test():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_stall(self):
@@ -613,7 +613,7 @@ def sim_test():
 
         sim = Simulator(dut)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_stall_compat(self):
@@ -638,7 +638,7 @@ def sim_test():
 
         sim = Simulator(dut)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
 
     def test_roundrobin(self):
@@ -700,5 +700,5 @@ def sim_test():
         sim = Simulator(dut)
         sim.add_clock(1e-6)
         sim.add_testbench(sim_test)
-        with sim.write_vcd(vcd_file=open("test.vcd", "w")):
+        with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()