diff --git a/tests/test_csr_action.py b/tests/test_csr_action.py index 5e31baa..6746a02 100644 --- a/tests/test_csr_action.py +++ b/tests/test_csr_action.py @@ -17,15 +17,14 @@ def test_simple(self): def test_sim(self): dut = action.R(unsigned(4)) - def process(): - yield dut.r_data.eq(0xa) - yield dut.port.r_stb.eq(1) - yield Delay() - self.assertEqual((yield dut.port.r_data), 0xa) - self.assertEqual((yield dut.r_stb), 1) + async def testbench(ctx): + ctx.set(dut.r_data, 0xa) + ctx.set(dut.port.r_stb, 1) + self.assertEqual(ctx.get(dut.port.r_data), 0xa) + self.assertEqual(ctx.get(dut.r_stb), 1) sim = Simulator(dut) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -40,15 +39,14 @@ def test_simple(self): def test_sim(self): dut = action.W(unsigned(4)) - def process(): - yield dut.port.w_data.eq(0xa) - yield dut.port.w_stb.eq(1) - yield Delay() - self.assertEqual((yield dut.w_data), 0xa) - self.assertEqual((yield dut.w_stb), 1) + async def testbench(ctx): + ctx.set(dut.port.w_data, 0xa) + ctx.set(dut.port.w_stb, 1) + self.assertEqual(ctx.get(dut.w_data), 0xa) + self.assertEqual(ctx.get(dut.w_stb), 1) sim = Simulator(dut) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -70,18 +68,18 @@ def test_simple(self): def test_sim(self): dut = action.RW(unsigned(4), init=0x5) - def process(): - self.assertEqual((yield dut.port.r_data), 0x5) - self.assertEqual((yield dut.data), 0x5) - yield dut.port.w_stb .eq(1) - yield dut.port.w_data.eq(0xa) - yield Tick() - self.assertEqual((yield dut.port.r_data), 0xa) - self.assertEqual((yield dut.data), 0xa) + async def testbench(ctx): + self.assertEqual(ctx.get(dut.port.r_data), 0x5) + self.assertEqual(ctx.get(dut.data), 0x5) + ctx.set(dut.port.w_stb, 1) + ctx.set(dut.port.w_data, 0xa) + await ctx.tick() + self.assertEqual(ctx.get(dut.port.r_data), 0xa) + self.assertEqual(ctx.get(dut.data), 0xa) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -105,24 +103,24 @@ def test_simple(self): def test_sim(self): dut = action.RW1C(unsigned(4), init=0xf) - def process(): - self.assertEqual((yield dut.port.r_data), 0xf) - self.assertEqual((yield dut.data), 0xf) - yield dut.port.w_stb .eq(1) - yield dut.port.w_data.eq(0x5) - yield Tick() - self.assertEqual((yield dut.port.r_data), 0xa) - self.assertEqual((yield dut.data), 0xa) - - yield dut.port.w_data.eq(0x3) - yield dut.set.eq(0x4) - yield Tick() - self.assertEqual((yield dut.port.r_data), 0xc) - self.assertEqual((yield dut.data), 0xc) + async def testbench(ctx): + self.assertEqual(ctx.get(dut.port.r_data), 0xf) + self.assertEqual(ctx.get(dut.data), 0xf) + ctx.set(dut.port.w_stb, 1) + ctx.set(dut.port.w_data, 0x5) + await ctx.tick() + self.assertEqual(ctx.get(dut.port.r_data), 0xa) + self.assertEqual(ctx.get(dut.data), 0xa) + + ctx.set(dut.port.w_data, 0x3) + ctx.set(dut.set, 0x4) + await ctx.tick() + self.assertEqual(ctx.get(dut.port.r_data), 0xc) + self.assertEqual(ctx.get(dut.data), 0xc) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -146,24 +144,24 @@ def test_simple(self): def test_sim(self): dut = action.RW1S(unsigned(4), init=0x5) - def process(): - self.assertEqual((yield dut.port.r_data), 0x5) - self.assertEqual((yield dut.data), 0x5) - yield dut.port.w_stb .eq(1) - yield dut.port.w_data.eq(0xa) - yield Tick() - self.assertEqual((yield dut.port.r_data), 0xf) - self.assertEqual((yield dut.data), 0xf) - - yield dut.port.w_data.eq(0x3) - yield dut.clear.eq(0x7) - yield Tick() - self.assertEqual((yield dut.port.r_data), 0xb) - self.assertEqual((yield dut.data), 0xb) + async def testbench(ctx): + self.assertEqual(ctx.get(dut.port.r_data), 0x5) + self.assertEqual(ctx.get(dut.data), 0x5) + ctx.set(dut.port.w_stb, 1) + ctx.set(dut.port.w_data, 0xa) + await ctx.tick() + self.assertEqual(ctx.get(dut.port.r_data), 0xf) + self.assertEqual(ctx.get(dut.data), 0xf) + + ctx.set(dut.port.w_data, 0x3) + ctx.set(dut.clear, 0x7) + await ctx.tick() + self.assertEqual(ctx.get(dut.port.r_data), 0xb) + self.assertEqual(ctx.get(dut.data), 0xb) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() diff --git a/tests/test_csr_bus.py b/tests/test_csr_bus.py index d45415e..db838b5 100644 --- a/tests/test_csr_bus.py +++ b/tests/test_csr_bus.py @@ -252,78 +252,76 @@ def test_sim(self): memory_map.add_resource(reg_16_rw, name=("reg_16_rw",), size=2) dut = csr.Multiplexer(memory_map, shadow_overlaps=shadow_overlaps) - bus = dut.bus - - def sim_test(): - yield reg_4_r.element.r_data.eq(0xa) - yield reg_16_rw.element.r_data.eq(0x5aa5) - - yield bus.addr.eq(0) - yield bus.r_stb.eq(1) - yield Tick() - self.assertEqual((yield reg_4_r.element.r_stb), 1) - self.assertEqual((yield reg_16_rw.element.r_stb), 0) - self.assertEqual((yield bus.r_data), 0xa) - - yield bus.addr.eq(2) - yield Tick() - self.assertEqual((yield reg_4_r.element.r_stb), 0) - self.assertEqual((yield reg_16_rw.element.r_stb), 1) - self.assertEqual((yield bus.r_data), 0xa5) - - yield bus.addr.eq(3) # pipeline a read - yield Tick() - self.assertEqual((yield reg_4_r.element.r_stb), 0) - self.assertEqual((yield reg_16_rw.element.r_stb), 0) - self.assertEqual((yield bus.r_data), 0x5a) - yield bus.r_stb.eq(0) - yield Delay() - - yield bus.addr.eq(1) - yield bus.w_data.eq(0x3d) - yield bus.w_stb.eq(1) - yield Tick() - self.assertEqual((yield reg_8_w.element.w_stb), 1) - self.assertEqual((yield reg_8_w.element.w_data), 0x3d) - self.assertEqual((yield reg_16_rw.element.w_stb), 0) - - yield bus.w_stb.eq(0) - yield bus.addr.eq(2) # change address - yield Tick() - self.assertEqual((yield reg_8_w.element.w_stb), 0) - - yield bus.addr.eq(2) - yield bus.w_data.eq(0x55) - yield bus.w_stb.eq(1) - yield Tick() - self.assertEqual((yield reg_8_w.element.w_stb), 0) - self.assertEqual((yield reg_16_rw.element.w_stb), 0) - yield bus.addr.eq(3) # pipeline a write - yield bus.w_data.eq(0xaa) - yield Tick() - self.assertEqual((yield reg_8_w.element.w_stb), 0) - self.assertEqual((yield reg_16_rw.element.w_stb), 1) - self.assertEqual((yield reg_16_rw.element.w_data), 0xaa55) - - yield bus.addr.eq(2) - yield bus.r_stb.eq(1) - yield bus.w_data.eq(0x66) - yield bus.w_stb.eq(1) - yield Tick() - self.assertEqual((yield reg_16_rw.element.r_stb), 1) - self.assertEqual((yield reg_16_rw.element.w_stb), 0) - self.assertEqual((yield bus.r_data), 0xa5) - yield bus.addr.eq(3) # pipeline a read and a write - yield bus.w_data.eq(0xbb) - yield Tick() - self.assertEqual((yield bus.r_data), 0x5a) - self.assertEqual((yield reg_16_rw.element.r_stb), 0) - self.assertEqual((yield reg_16_rw.element.w_stb), 1) - self.assertEqual((yield reg_16_rw.element.w_data), 0xbb66) + + async def testbench(ctx): + ctx.set(reg_4_r.element.r_data, 0xa) + ctx.set(reg_16_rw.element.r_data, 0x5aa5) + + ctx.set(dut.bus.addr, 0) + ctx.set(dut.bus.r_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(reg_4_r.element.r_stb), 1) + self.assertEqual(ctx.get(reg_16_rw.element.r_stb), 0) + self.assertEqual(ctx.get(dut.bus.r_data), 0xa) + + ctx.set(dut.bus.addr, 2) + await ctx.tick() + self.assertEqual(ctx.get(reg_4_r.element.r_stb), 0) + self.assertEqual(ctx.get(reg_16_rw.element.r_stb), 1) + self.assertEqual(ctx.get(dut.bus.r_data), 0xa5) + + ctx.set(dut.bus.addr, 3) # pipeline a read + await ctx.tick() + self.assertEqual(ctx.get(reg_4_r.element.r_stb), 0) + self.assertEqual(ctx.get(reg_16_rw.element.r_stb), 0) + self.assertEqual(ctx.get(dut.bus.r_data), 0x5a) + ctx.set(dut.bus.r_stb, 0) + + ctx.set(dut.bus.addr, 1) + ctx.set(dut.bus.w_data, 0x3d) + ctx.set(dut.bus.w_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(reg_8_w.element.w_stb), 1) + self.assertEqual(ctx.get(reg_8_w.element.w_data), 0x3d) + self.assertEqual(ctx.get(reg_16_rw.element.w_stb), 0) + + ctx.set(dut.bus.w_stb, 0) + ctx.set(dut.bus.addr, 2) # change address + await ctx.tick() + self.assertEqual(ctx.get(reg_8_w.element.w_stb), 0) + + ctx.set(dut.bus.addr, 2) + ctx.set(dut.bus.w_data, 0x55) + ctx.set(dut.bus.w_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(reg_8_w.element.w_stb), 0) + self.assertEqual(ctx.get(reg_16_rw.element.w_stb), 0) + ctx.set(dut.bus.addr, 3) # pipeline a write + ctx.set(dut.bus.w_data, 0xaa) + await ctx.tick() + self.assertEqual(ctx.get(reg_8_w.element.w_stb), 0) + self.assertEqual(ctx.get(reg_16_rw.element.w_stb), 1) + self.assertEqual(ctx.get(reg_16_rw.element.w_data), 0xaa55) + + ctx.set(dut.bus.addr, 2) + ctx.set(dut.bus.r_stb, 1) + ctx.set(dut.bus.w_data, 0x66) + ctx.set(dut.bus.w_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(reg_16_rw.element.r_stb), 1) + self.assertEqual(ctx.get(reg_16_rw.element.w_stb), 0) + self.assertEqual(ctx.get(dut.bus.r_data), 0xa5) + ctx.set(dut.bus.addr, 3) # pipeline a read and a write + ctx.set(dut.bus.w_data, 0xbb) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0x5a) + self.assertEqual(ctx.get(reg_16_rw.element.r_stb), 0) + self.assertEqual(ctx.get(reg_16_rw.element.w_stb), 1) + self.assertEqual(ctx.get(reg_16_rw.element.w_data), 0xbb66) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -337,31 +335,30 @@ def test_sim(self): memory_map.add_resource(reg_20_rw, name=("reg_20_rw",), size=3) dut = csr.Multiplexer(memory_map, shadow_overlaps=shadow_overlaps) - bus = dut.bus - - def sim_test(): - yield bus.w_stb.eq(1) - yield bus.addr.eq(0) - yield bus.w_data.eq(0x55) - yield Tick() - self.assertEqual((yield reg_20_rw.element.w_stb), 0) - yield bus.addr.eq(1) - yield bus.w_data.eq(0xaa) - yield Tick() - self.assertEqual((yield reg_20_rw.element.w_stb), 0) - yield bus.addr.eq(2) - yield bus.w_data.eq(0x33) - yield Tick() - self.assertEqual((yield reg_20_rw.element.w_stb), 0) - yield bus.addr.eq(3) - yield bus.w_data.eq(0xdd) - yield Tick() - self.assertEqual((yield reg_20_rw.element.w_stb), 1) - self.assertEqual((yield reg_20_rw.element.w_data), 0x3aa55) + + async def testbench(ctx): + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.addr, 0) + ctx.set(dut.bus.w_data, 0x55) + await ctx.tick() + self.assertEqual(ctx.get(reg_20_rw.element.w_stb), 0) + ctx.set(dut.bus.addr, 1) + ctx.set(dut.bus.w_data, 0xaa) + await ctx.tick() + self.assertEqual(ctx.get(reg_20_rw.element.w_stb), 0) + ctx.set(dut.bus.addr, 2) + ctx.set(dut.bus.w_data, 0x33) + await ctx.tick() + self.assertEqual(ctx.get(reg_20_rw.element.w_stb), 0) + ctx.set(dut.bus.addr, 3) + ctx.set(dut.bus.w_data, 0xdd) + await ctx.tick() + self.assertEqual(ctx.get(reg_20_rw.element.w_stb), 1) + self.assertEqual(ctx.get(reg_20_rw.element.w_data), 0x3aa55) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -427,41 +424,41 @@ def test_sim(self): self.assertEqual(reg_1_addr, 0x0000) self.assertEqual(reg_2_addr, 0x0402) - bus = self.dut.bus - - def sim_test(): - yield bus.addr.eq(reg_1_addr) - yield bus.w_stb.eq(1) - yield bus.w_data.eq(0x55) - yield Tick() - yield bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_1.element.w_data), 0x55) - - yield bus.addr.eq(reg_2_addr) - yield bus.w_stb.eq(1) - yield bus.w_data.eq(0xaa) - yield Tick() - yield bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_2.element.w_data), 0xaa) - - yield reg_1.element.r_data.eq(0x55) - yield reg_2.element.r_data.eq(0xaa) - - yield bus.addr.eq(reg_1_addr) - yield bus.r_stb.eq(1) - yield Tick() - yield bus.addr.eq(reg_2_addr) - yield Delay() - self.assertEqual((yield bus.r_data), 0x55) - yield Tick() - self.assertEqual((yield bus.r_data), 0xaa) + async def testbench(ctx): + ctx.set(self.dut.bus.addr, reg_1_addr) + ctx.set(self.dut.bus.w_stb, 1) + ctx.set(self.dut.bus.w_data, 0x55) + await ctx.tick() + ctx.set(self.dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_1.element.w_data), 0x55) + + ctx.set(self.dut.bus.addr, reg_2_addr) + ctx.set(self.dut.bus.w_stb, 1) + ctx.set(self.dut.bus.w_data, 0xaa) + await ctx.tick() + ctx.set(self.dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_2.element.w_data), 0xaa) + + ctx.set(reg_1.element.r_data, 0x55) + ctx.set(reg_2.element.r_data, 0xaa) + + ctx.set(self.dut.bus.addr, reg_1_addr) + ctx.set(self.dut.bus.r_stb, 1) + await ctx.tick() + ctx.set(self.dut.bus.addr, reg_2_addr) + self.assertEqual(ctx.get(self.dut.bus.r_data), 0x55) + await ctx.tick() + self.assertEqual(ctx.get(self.dut.bus.r_data), 0xaa) m = Module() - m.submodules += self.dut, mux_1, mux_2 + m.submodules.dut = self.dut + m.submodules.mux_1 = mux_1 + m.submodules.mux_2 = mux_2 + sim = Simulator(m) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() diff --git a/tests/test_csr_event.py b/tests/test_csr_event.py index f24601d..2517bce 100644 --- a/tests/test_csr_event.py +++ b/tests/test_csr_event.py @@ -8,14 +8,6 @@ from amaranth_soc import event -def simulation_test(dut, process): - sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_testbench(process) - with sim.write_vcd(vcd_file="test.vcd"): - sim.run() - - class EventMonitorTestCase(unittest.TestCase): def test_params(self): event_map = event.EventMap() @@ -76,50 +68,51 @@ def test_simple(self): addr_enable = 0x0 addr_pending = 0x1 - def process(): - yield sub.i.eq(1) - yield Delay() - self.assertEqual((yield sub.trg), 1) - self.assertEqual((yield dut.src.i), 0) - - yield dut.bus.addr.eq(addr_enable) - yield dut.bus.r_stb.eq(1) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0b0) - yield dut.bus.r_stb.eq(0) - yield Delay() - - yield dut.bus.addr.eq(addr_enable) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0b1) - yield Tick() - yield dut.bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield dut.src.i), 1) - - yield sub.i.eq(0) - yield Delay() - self.assertEqual((yield sub.trg), 0) - - yield dut.bus.addr.eq(addr_pending) - yield dut.bus.r_stb.eq(1) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0b1) - yield dut.bus.r_stb.eq(0) - yield Delay() - - yield dut.bus.addr.eq(addr_pending) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0b1) - yield Tick() - yield dut.bus.w_stb.eq(0) - yield Tick() - - yield dut.bus.addr.eq(addr_pending) - yield dut.bus.r_stb.eq(1) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0b0) - yield dut.bus.r_stb.eq(0) - yield Delay() - - simulation_test(dut, process) + async def testbench(ctx): + ctx.set(sub.i, 1) + self.assertEqual(ctx.get(sub.trg), 1) + self.assertEqual(ctx.get(dut.src.i), 0) + + ctx.set(dut.bus.addr, addr_enable) + ctx.set(dut.bus.r_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0b0) + ctx.set(dut.bus.r_stb, 0) + + ctx.set(dut.bus.addr, addr_enable) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0b1) + await ctx.tick() + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.src.i), 1) + + ctx.set(sub.i, 0) + self.assertEqual(ctx.get(sub.trg), 0) + + ctx.set(dut.bus.addr, addr_pending) + ctx.set(dut.bus.r_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0b1) + ctx.set(dut.bus.r_stb, 0) + + ctx.set(dut.bus.addr, addr_pending) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0b1) + await ctx.tick() + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + + ctx.set(dut.bus.addr, addr_pending) + ctx.set(dut.bus.r_stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0b0) + ctx.set(dut.bus.r_stb, 0) + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_testbench(testbench) + with sim.write_vcd(vcd_file="test.vcd"): + sim.run() + + diff --git a/tests/test_csr_reg.py b/tests/test_csr_reg.py index 02a04ce..765db46 100644 --- a/tests/test_csr_reg.py +++ b/tests/test_csr_reg.py @@ -523,72 +523,68 @@ class FooRegister(Register, access="rw"): dut = FooRegister() - def process(): + async def testbench(ctx): # Check init values: - self.assertEqual((yield dut.f.b .data), 0b111) - self.assertEqual((yield dut.f.c.d.data), -1) - self.assertEqual((yield dut.f.f .data), 0b000) + self.assertEqual(ctx.get(dut.f.b .data), 0b111) + self.assertEqual(ctx.get(dut.f.c.d.data), -1) + self.assertEqual(ctx.get(dut.f.f .data), 0b000) - self.assertEqual((yield dut.f.b .port.r_data), 0b111) - self.assertEqual((yield dut.f.c.d .port.r_data), -1) - self.assertEqual((yield dut.f.f .port.r_data), 0b000) + self.assertEqual(ctx.get(dut.f.b .port.r_data), 0b111) + self.assertEqual(ctx.get(dut.f.c.d .port.r_data), -1) + self.assertEqual(ctx.get(dut.f.f .port.r_data), 0b000) # Initiator read: - yield dut.element.r_stb.eq(1) - yield Delay() + ctx.set(dut.element.r_stb, 1) - self.assertEqual((yield dut.f.a.port.r_stb), 1) - self.assertEqual((yield dut.f.b.port.r_stb), 1) - self.assertEqual((yield dut.f.f.port.r_stb), 1) + self.assertEqual(ctx.get(dut.f.a.port.r_stb), 1) + self.assertEqual(ctx.get(dut.f.b.port.r_stb), 1) + self.assertEqual(ctx.get(dut.f.f.port.r_stb), 1) - yield dut.element.r_stb.eq(0) + ctx.set(dut.element.r_stb, 0) # Initiator write: - yield dut.element.w_stb .eq(1) - yield dut.element.w_data.eq(Cat( + ctx.set(dut.element.w_stb, 1) + ctx.set(dut.element.w_data, Cat( Const(0b1, 1), # a Const(0b010, 3), # b Const(0b00, 2), # c.d Const(0b00, 2), # e Const(0b110, 3), # f )) - yield Delay() - self.assertEqual((yield dut.f.a .port.w_stb), 0) - self.assertEqual((yield dut.f.b .port.w_stb), 1) - self.assertEqual((yield dut.f.c.d .port.w_stb), 1) - self.assertEqual((yield dut.f.e[0].port.w_stb), 1) - self.assertEqual((yield dut.f.e[1].port.w_stb), 1) - self.assertEqual((yield dut.f.f .port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.a .port.w_stb), 0) + self.assertEqual(ctx.get(dut.f.b .port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.c.d .port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.e[0].port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.e[1].port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.f .port.w_stb), 1) - self.assertEqual((yield dut.f.b .port.w_data), 0b010) - self.assertEqual((yield dut.f.c.d .port.w_data), 0b00) - self.assertEqual((yield dut.f.e[0].port.w_data), 0b0) - self.assertEqual((yield dut.f.e[1].port.w_data), 0b0) - self.assertEqual((yield dut.f.f .port.w_data), 0b110) + self.assertEqual(ctx.get(dut.f.b .port.w_data), 0b010) + self.assertEqual(ctx.get(dut.f.c.d .port.w_data), 0b00) + self.assertEqual(ctx.get(dut.f.e[0].port.w_data), 0b0) + self.assertEqual(ctx.get(dut.f.e[1].port.w_data), 0b0) + self.assertEqual(ctx.get(dut.f.f .port.w_data), 0b110) - self.assertEqual((yield dut.f.e[0].w_data), 0b0) - self.assertEqual((yield dut.f.e[1].w_data), 0b0) + self.assertEqual(ctx.get(dut.f.e[0].w_data), 0b0) + self.assertEqual(ctx.get(dut.f.e[1].w_data), 0b0) - yield Tick() - yield dut.element.w_stb.eq(0) - yield Delay() + await ctx.tick() + ctx.set(dut.element.w_stb, 0) - self.assertEqual((yield dut.f.b .data), 0b101) - self.assertEqual((yield dut.f.c.d.data), 0b00) - self.assertEqual((yield dut.f.f .data), 0b110) + self.assertEqual(ctx.get(dut.f.b .data), 0b101) + self.assertEqual(ctx.get(dut.f.c.d.data), 0b00) + self.assertEqual(ctx.get(dut.f.f .data), 0b110) # User write: - yield dut.f.a.r_data.eq(0b1) - yield dut.f.b.set .eq(0b010) - yield dut.f.f.clear .eq(0b010) - yield Delay() + ctx.set(dut.f.a.r_data, 0b1) + ctx.set(dut.f.b.set, 0b010) + ctx.set(dut.f.f.clear, 0b010) - self.assertEqual((yield dut.element.r_data), + self.assertEqual(ctx.get(dut.element.r_data), Const.cast(Cat( Const(0b1, 1), # a Const(0b101, 3), # b @@ -597,13 +593,12 @@ def process(): Const(0b110, 3), # f )).value) - yield Tick() - yield dut.f.a.r_data.eq(0b0) - yield dut.f.b.set .eq(0b000) - yield dut.f.f.clear .eq(0b000) - yield Delay() + await ctx.tick() + ctx.set(dut.f.a.r_data, 0b0) + ctx.set(dut.f.b.set, 0b000) + ctx.set(dut.f.f.clear, 0b000) - self.assertEqual((yield dut.element.r_data), + self.assertEqual(ctx.get(dut.element.r_data), Const.cast(Cat( Const(0b0, 1), # a Const(0b111, 3), # b @@ -614,8 +609,8 @@ def process(): # Concurrent writes: - yield dut.element.w_stb .eq(1) - yield dut.element.w_data.eq(Cat( + ctx.set(dut.element.w_stb, 1) + ctx.set(dut.element.w_data, Cat( Const(0b0, 1), # a Const(0b111, 3), # b Const(0b00, 2), # c.d @@ -623,11 +618,11 @@ def process(): Const(0b111, 3), # f )) - yield dut.f.b.set .eq(0b001) - yield dut.f.f.clear.eq(0b111) - yield Tick() + ctx.set(dut.f.b.set, 0b001) + ctx.set(dut.f.f.clear, 0b111) + await ctx.tick() - self.assertEqual((yield dut.element.r_data), + self.assertEqual(ctx.get(dut.element.r_data), Const.cast(Cat( Const(0b0, 1), # a Const(0b001, 3), # b @@ -636,51 +631,45 @@ def process(): Const(0b111, 3), # f )).value) - self.assertEqual((yield dut.f.b.data), 0b001) - self.assertEqual((yield dut.f.f.data), 0b111) + self.assertEqual(ctx.get(dut.f.b.data), 0b001) + self.assertEqual(ctx.get(dut.f.f.data), 0b111) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() def test_sim_single(self): dut = Register(Field(action.RW, unsigned(1), init=1), access="rw") - def process(): + async def testbench(ctx): # Check init values: - self.assertEqual((yield dut.f.data), 1) - self.assertEqual((yield dut.f.port.r_data), 1) + self.assertEqual(ctx.get(dut.f.data), 1) + self.assertEqual(ctx.get(dut.f.port.r_data), 1) # Initiator read: - yield dut.element.r_stb.eq(1) - yield Delay() - - self.assertEqual((yield dut.f.port.r_stb), 1) - - yield dut.element.r_stb.eq(0) + ctx.set(dut.element.r_stb, 1) + self.assertEqual(ctx.get(dut.f.port.r_stb), 1) + ctx.set(dut.element.r_stb, 0) # Initiator write: - yield dut.element.w_stb.eq(1) - yield dut.element.w_data.eq(0) - yield Delay() - - self.assertEqual((yield dut.f.port.w_stb), 1) - self.assertEqual((yield dut.f.port.w_data), 0) + ctx.set(dut.element.w_stb, 1) + ctx.set(dut.element.w_data, 0) - yield Tick() - yield dut.element.w_stb.eq(0) - yield Delay() + self.assertEqual(ctx.get(dut.f.port.w_stb), 1) + self.assertEqual(ctx.get(dut.f.port.w_data), 0) - self.assertEqual((yield dut.f.data), 0) + await ctx.tick() + ctx.set(dut.element.w_stb, 0) + self.assertEqual(ctx.get(dut.f.data), 0) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -978,77 +967,77 @@ def test_sim(self): dut = Bridge(regs.as_memory_map()) - def process(): - yield dut.bus.addr.eq(0) - yield dut.bus.r_stb.eq(1) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0xa) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0x0) - self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 1) - self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_4 .f.a.port.w_stb), 1) - self.assertEqual((yield reg_rw_8 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0) - yield dut.bus.r_stb.eq(0) - yield dut.bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_rw_4.f.a.data), 0xa) - - yield dut.bus.addr.eq(1) - yield dut.bus.r_stb.eq(1) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0xbb) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0x11) - self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 1) - self.assertEqual((yield reg_rw_16.f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_4 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.w_stb), 1) - self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0) - yield dut.bus.r_stb.eq(0) - yield dut.bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_rw_8.f.a.data), 0xbb) - - yield dut.bus.addr.eq(2) - yield dut.bus.r_stb.eq(1) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0xcc) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0x22) - self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.r_stb), 1) - self.assertEqual((yield reg_rw_4 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0) - yield dut.bus.r_stb.eq(0) - yield dut.bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_rw_16.f.a.data), 0x3322) - - yield dut.bus.addr.eq(3) - yield dut.bus.r_stb.eq(1) - yield dut.bus.w_stb.eq(1) - yield dut.bus.w_data.eq(0xdd) - yield Tick() - self.assertEqual((yield dut.bus.r_data), 0x33) - self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.r_stb), 0) - self.assertEqual((yield reg_rw_4 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_8 .f.a.port.w_stb), 0) - self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 1) - yield dut.bus.r_stb.eq(0) - yield dut.bus.w_stb.eq(0) - yield Tick() - self.assertEqual((yield reg_rw_16.f.a.data), 0xddcc) + async def testbench(ctx): + ctx.set(dut.bus.addr, 0) + ctx.set(dut.bus.r_stb, 1) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0xa) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0x0) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.r_stb), 1) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.w_stb), 1) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.w_stb), 0) + ctx.set(dut.bus.r_stb, 0) + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_rw_4.f.a.data), 0xa) + + ctx.set(dut.bus.addr, 1) + ctx.set(dut.bus.r_stb, 1) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0xbb) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0x11) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.r_stb), 1) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.w_stb), 1) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.w_stb), 0) + ctx.set(dut.bus.r_stb, 0) + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_rw_8.f.a.data), 0xbb) + + ctx.set(dut.bus.addr, 2) + ctx.set(dut.bus.r_stb, 1) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0xcc) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0x22) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.r_stb), 1) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.w_stb), 0) + ctx.set(dut.bus.r_stb, 0) + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_rw_16.f.a.data), 0x3322) + + ctx.set(dut.bus.addr, 3) + ctx.set(dut.bus.r_stb, 1) + ctx.set(dut.bus.w_stb, 1) + ctx.set(dut.bus.w_data, 0xdd) + await ctx.tick() + self.assertEqual(ctx.get(dut.bus.r_data), 0x33) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.r_stb), 0) + self.assertEqual(ctx.get(reg_rw_4 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_8 .f.a.port.w_stb), 0) + self.assertEqual(ctx.get(reg_rw_16.f.a.port.w_stb), 1) + ctx.set(dut.bus.r_stb, 0) + ctx.set(dut.bus.w_stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(reg_rw_16.f.a.data), 0xddcc) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(process) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() diff --git a/tests/test_csr_wishbone.py b/tests/test_csr_wishbone.py index 717156e..a437c07 100644 --- a/tests/test_csr_wishbone.py +++ b/tests/test_csr_wishbone.py @@ -61,96 +61,93 @@ def test_narrow(self): mux = csr.Multiplexer(memory_map) dut = WishboneCSRBridge(mux.bus) - def sim_test(): - yield dut.wb_bus.cyc.eq(1) - yield dut.wb_bus.sel.eq(0b1) - - yield dut.wb_bus.we.eq(1) - - yield dut.wb_bus.adr.eq(0) - yield dut.wb_bus.stb.eq(1) - yield dut.wb_bus.dat_w.eq(0x55) - for _ in range(2): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_1.r_count), 0) - self.assertEqual((yield reg_1.w_count), 1) - self.assertEqual((yield reg_1.data), 0x55) - - yield dut.wb_bus.adr.eq(1) - yield dut.wb_bus.stb.eq(1) - yield dut.wb_bus.dat_w.eq(0xaa) - for _ in range(2): - yield Tick() - yield dut.wb_bus.stb.eq(0) - self.assertEqual((yield dut.wb_bus.ack), 1) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_2.r_count), 0) - self.assertEqual((yield reg_2.w_count), 0) - self.assertEqual((yield reg_2.data), 0) - - yield dut.wb_bus.adr.eq(2) - yield dut.wb_bus.stb.eq(1) - yield dut.wb_bus.dat_w.eq(0xbb) - for _ in range(2): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_2.r_count), 0) - self.assertEqual((yield reg_2.w_count), 1) - self.assertEqual((yield reg_2.data), 0xbbaa) - - yield dut.wb_bus.we.eq(0) - - yield dut.wb_bus.adr.eq(0) - yield dut.wb_bus.stb.eq(1) - for _ in range(2): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - self.assertEqual((yield dut.wb_bus.dat_r), 0x55) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_1.r_count), 1) - self.assertEqual((yield reg_1.w_count), 1) - - yield dut.wb_bus.adr.eq(1) - yield dut.wb_bus.stb.eq(1) - for _ in range(2): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - self.assertEqual((yield dut.wb_bus.dat_r), 0xaa) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_2.r_count), 1) - self.assertEqual((yield reg_2.w_count), 1) - - yield reg_2.data.eq(0x33333) - - yield dut.wb_bus.adr.eq(2) - yield dut.wb_bus.stb.eq(1) - for _ in range(2): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - self.assertEqual((yield dut.wb_bus.dat_r), 0xbb) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg_2.r_count), 1) - self.assertEqual((yield reg_2.w_count), 1) + async def testbench(ctx): + ctx.set(dut.wb_bus.cyc, 1) + ctx.set(dut.wb_bus.sel, 0b1) + ctx.set(dut.wb_bus.we, 1) + + ctx.set(dut.wb_bus.adr, 0) + ctx.set(dut.wb_bus.stb, 1) + ctx.set(dut.wb_bus.dat_w, 0x55) + await ctx.tick().repeat(2) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_1.r_count), 0) + self.assertEqual(ctx.get(reg_1.w_count), 1) + self.assertEqual(ctx.get(reg_1.data), 0x55) + + ctx.set(dut.wb_bus.adr, 1) + ctx.set(dut.wb_bus.stb, 1) + ctx.set(dut.wb_bus.dat_w, 0xaa) + await ctx.tick().repeat(2) + ctx.set(dut.wb_bus.stb, 0) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_2.r_count), 0) + self.assertEqual(ctx.get(reg_2.w_count), 0) + self.assertEqual(ctx.get(reg_2.data), 0) + + ctx.set(dut.wb_bus.adr, 2) + ctx.set(dut.wb_bus.stb, 1) + ctx.set(dut.wb_bus.dat_w, 0xbb) + await ctx.tick().repeat(2) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_2.r_count), 0) + self.assertEqual(ctx.get(reg_2.w_count), 1) + self.assertEqual(ctx.get(reg_2.data), 0xbbaa) + + ctx.set(dut.wb_bus.we, 0) + + ctx.set(dut.wb_bus.adr, 0) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(2) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + self.assertEqual(ctx.get(dut.wb_bus.dat_r), 0x55) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_1.r_count), 1) + self.assertEqual(ctx.get(reg_1.w_count), 1) + + ctx.set(dut.wb_bus.adr, 1) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(2) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + self.assertEqual(ctx.get(dut.wb_bus.dat_r), 0xaa) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_2.r_count), 1) + self.assertEqual(ctx.get(reg_2.w_count), 1) + + ctx.set(reg_2.data, 0x33333) + + ctx.set(dut.wb_bus.adr, 2) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(2) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + self.assertEqual(ctx.get(dut.wb_bus.dat_r), 0xbb) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg_2.r_count), 1) + self.assertEqual(ctx.get(reg_2.w_count), 1) m = Module() - m.submodules += mux, reg_1, reg_2, dut + m.submodules.reg_1 = reg_1 + m.submodules.reg_2 = reg_2 + m.submodules.mux = mux + m.submodules.dut = dut + sim = Simulator(m) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -163,72 +160,70 @@ def test_wide(self): mux = csr.Multiplexer(memory_map) dut = WishboneCSRBridge(mux.bus, data_width=32) - def sim_test(): - yield dut.wb_bus.cyc.eq(1) - yield dut.wb_bus.adr.eq(0) - - yield dut.wb_bus.we.eq(1) - - yield dut.wb_bus.dat_w.eq(0x44332211) - yield dut.wb_bus.sel.eq(0b1111) - yield dut.wb_bus.stb.eq(1) - for _ in range(5): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg.r_count), 0) - self.assertEqual((yield reg.w_count), 1) - self.assertEqual((yield reg.data), 0x44332211) + async def testbench(ctx): + ctx.set(dut.wb_bus.cyc, 1) + ctx.set(dut.wb_bus.adr, 0) + ctx.set(dut.wb_bus.we, 1) + + ctx.set(dut.wb_bus.dat_w, 0x44332211) + ctx.set(dut.wb_bus.sel, 0b1111) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(5) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg.r_count), 0) + self.assertEqual(ctx.get(reg.w_count), 1) + self.assertEqual(ctx.get(reg.data), 0x44332211) # partial write - yield dut.wb_bus.dat_w.eq(0xaabbccdd) - yield dut.wb_bus.sel.eq(0b0110) - yield dut.wb_bus.stb.eq(1) - for _ in range(5): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg.r_count), 0) - self.assertEqual((yield reg.w_count), 1) - self.assertEqual((yield reg.data), 0x44332211) - - yield dut.wb_bus.we.eq(0) - - yield dut.wb_bus.sel.eq(0b1111) - yield dut.wb_bus.stb.eq(1) - for _ in range(5): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - self.assertEqual((yield dut.wb_bus.dat_r), 0x44332211) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg.r_count), 1) - self.assertEqual((yield reg.w_count), 1) - - yield reg.data.eq(0xaaaaaaaa) + ctx.set(dut.wb_bus.dat_w, 0xaabbccdd) + ctx.set(dut.wb_bus.sel, 0b0110) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(5) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg.r_count), 0) + self.assertEqual(ctx.get(reg.w_count), 1) + self.assertEqual(ctx.get(reg.data), 0x44332211) + + ctx.set(dut.wb_bus.we, 0) + + ctx.set(dut.wb_bus.sel, 0b1111) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(5) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + self.assertEqual(ctx.get(dut.wb_bus.dat_r), 0x44332211) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg.r_count), 1) + self.assertEqual(ctx.get(reg.w_count), 1) + + ctx.set(reg.data, 0xaaaaaaaa) # partial read - yield dut.wb_bus.sel.eq(0b0110) - yield dut.wb_bus.stb.eq(1) - for _ in range(5): - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 1) - self.assertEqual((yield dut.wb_bus.dat_r), 0x00332200) - yield dut.wb_bus.stb.eq(0) - yield Tick() - self.assertEqual((yield dut.wb_bus.ack), 0) - self.assertEqual((yield reg.r_count), 1) - self.assertEqual((yield reg.w_count), 1) + ctx.set(dut.wb_bus.sel, 0b0110) + ctx.set(dut.wb_bus.stb, 1) + await ctx.tick().repeat(5) + self.assertEqual(ctx.get(dut.wb_bus.ack), 1) + self.assertEqual(ctx.get(dut.wb_bus.dat_r), 0x00332200) + ctx.set(dut.wb_bus.stb, 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.wb_bus.ack), 0) + self.assertEqual(ctx.get(reg.r_count), 1) + self.assertEqual(ctx.get(reg.w_count), 1) m = Module() - m.submodules += mux, reg, dut + m.submodules.reg = reg + m.submodules.mux = mux + m.submodules.dut = dut + sim = Simulator(m) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() diff --git a/tests/test_event.py b/tests/test_event.py index ce90a73..bf988c9 100644 --- a/tests/test_event.py +++ b/tests/test_event.py @@ -8,14 +8,6 @@ from amaranth_soc import event -def simulation_test(dut, process): - sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_testbench(process) - with sim.write_vcd(vcd_file="test.vcd"): - sim.run() - - class SourceSignatureTestCase(unittest.TestCase): def test_level(self): sig = event.Source.Signature(trigger="level") @@ -186,60 +178,60 @@ def test_events(self): event_map.add(sub_2) dut = event.Monitor(event_map) - def process(): - yield sub_0.i.eq(1) - yield sub_1.i.eq(0) - yield sub_2.i.eq(1) - yield Tick() - self.assertEqual((yield sub_0.trg), 1) - self.assertEqual((yield sub_1.trg), 0) - self.assertEqual((yield sub_2.trg), 0) - self.assertEqual((yield dut.pending), 0b001) - self.assertEqual((yield dut.src.i), 0) - - yield dut.enable.eq(0b111) - yield Tick() - self.assertEqual((yield dut.src.i), 1) - - yield dut.clear.eq(0b001) - yield Tick() - self.assertEqual((yield dut.pending), 0b001) - self.assertEqual((yield dut.src.i), 1) - - yield sub_0.i.eq(0) - yield Delay() - self.assertEqual((yield sub_0.trg), 0) - self.assertEqual((yield sub_1.trg), 0) - self.assertEqual((yield sub_2.trg), 0) - yield Tick() - self.assertEqual((yield dut.pending), 0b000) - self.assertEqual((yield dut.src.i), 0) - - yield sub_1.i.eq(1) - yield Delay() - self.assertEqual((yield sub_0.trg), 0) - self.assertEqual((yield sub_1.trg), 1) - self.assertEqual((yield sub_2.trg), 0) - yield Tick() - self.assertEqual((yield dut.pending), 0b010) - self.assertEqual((yield dut.src.i), 1) - - yield sub_2.i.eq(0) - yield Delay() - self.assertEqual((yield sub_0.trg), 0) - self.assertEqual((yield sub_1.trg), 0) - self.assertEqual((yield sub_2.trg), 1) - yield Tick() - self.assertEqual((yield dut.pending), 0b110) - self.assertEqual((yield dut.src.i), 1) - - yield dut.clear.eq(0b110) - yield Delay() - self.assertEqual((yield sub_0.trg), 0) - self.assertEqual((yield sub_1.trg), 0) - self.assertEqual((yield sub_2.trg), 0) - yield Tick() - self.assertEqual((yield dut.pending), 0b000) - self.assertEqual((yield dut.src.i), 0) - - simulation_test(dut, process) + async def testbench(ctx): + ctx.set(sub_0.i, 1) + ctx.set(sub_1.i, 0) + ctx.set(sub_2.i, 1) + await ctx.tick() + self.assertEqual(ctx.get(sub_0.trg), 1) + self.assertEqual(ctx.get(sub_1.trg), 0) + self.assertEqual(ctx.get(sub_2.trg), 0) + self.assertEqual(ctx.get(dut.pending), 0b001) + self.assertEqual(ctx.get(dut.src.i), 0) + + ctx.set(dut.enable, 0b111) + await ctx.tick() + self.assertEqual(ctx.get(dut.src.i), 1) + + ctx.set(dut.clear, 0b001) + await ctx.tick() + self.assertEqual(ctx.get(dut.pending), 0b001) + self.assertEqual(ctx.get(dut.src.i), 1) + + ctx.set(sub_0.i, 0) + self.assertEqual(ctx.get(sub_0.trg), 0) + self.assertEqual(ctx.get(sub_1.trg), 0) + self.assertEqual(ctx.get(sub_2.trg), 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.pending), 0b000) + self.assertEqual(ctx.get(dut.src.i), 0) + + ctx.set(sub_1.i, 1) + self.assertEqual(ctx.get(sub_0.trg), 0) + self.assertEqual(ctx.get(sub_1.trg), 1) + self.assertEqual(ctx.get(sub_2.trg), 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.pending), 0b010) + self.assertEqual(ctx.get(dut.src.i), 1) + + ctx.set(sub_2.i, 0) + self.assertEqual(ctx.get(sub_0.trg), 0) + self.assertEqual(ctx.get(sub_1.trg), 0) + self.assertEqual(ctx.get(sub_2.trg), 1) + await ctx.tick() + self.assertEqual(ctx.get(dut.pending), 0b110) + self.assertEqual(ctx.get(dut.src.i), 1) + + ctx.set(dut.clear, 0b110) + self.assertEqual(ctx.get(sub_0.trg), 0) + self.assertEqual(ctx.get(sub_1.trg), 0) + self.assertEqual(ctx.get(sub_2.trg), 0) + await ctx.tick() + self.assertEqual(ctx.get(dut.pending), 0b000) + self.assertEqual(ctx.get(dut.src.i), 0) + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_testbench(testbench) + with sim.write_vcd(vcd_file="test.vcd"): + sim.run() diff --git a/tests/test_gpio.py b/tests/test_gpio.py index a1ed014..b5e4172 100644 --- a/tests/test_gpio.py +++ b/tests/test_gpio.py @@ -36,16 +36,16 @@ def test_init_wrong_input_stages(self): r"Input stages must be a non-negative integer, not -1"): gpio.Peripheral(pin_count=1, addr_width=2, data_width=8, input_stages=-1) - def _csr_access(self, dut, addr, r_stb=0, w_stb=0, w_data=0, r_data=0): - yield dut.bus.addr.eq(addr) - yield dut.bus.r_stb.eq(r_stb) - yield dut.bus.w_stb.eq(w_stb) - yield dut.bus.w_data.eq(w_data) - yield Tick() + async def _csr_access(self, ctx, dut, addr, r_stb=0, w_stb=0, w_data=0, r_data=0): + ctx.set(dut.bus.addr, addr) + ctx.set(dut.bus.r_stb, r_stb) + ctx.set(dut.bus.w_stb, w_stb) + ctx.set(dut.bus.w_data, w_data) + await ctx.tick() if r_stb: - self.assertEqual((yield dut.bus.r_data), r_data) - yield dut.bus.r_stb.eq(0) - yield dut.bus.w_stb.eq(0) + self.assertEqual(ctx.get(dut.bus.r_data), r_data) + ctx.set(dut.bus.r_stb, 0) + ctx.set(dut.bus.w_stb, 0) def test_sim(self): dut = gpio.Peripheral(pin_count=4, addr_width=2, data_width=8) @@ -55,277 +55,277 @@ def test_sim(self): output_addr = 0x2 setclr_addr = 0x3 - def testbench(): + async def testbench(ctx): # INPUT_ONLY mode ===================================================================== # - read Mode: - yield from self._csr_access(dut, mode_addr, r_stb=1, r_data=0b00000000) + await self._csr_access(ctx, dut, mode_addr, r_stb=1, r_data=0b00000000) for n in range(4): - self.assertEqual((yield dut.alt_mode[n]), 0) - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.alt_mode[n]), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - read Input: - yield dut.pins[1].i.eq(1) - yield dut.pins[3].i.eq(1) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield dut.pins[1].i.eq(0) - yield dut.pins[3].i.eq(0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0xa) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 1) + ctx.set(dut.pins[3].i, 1) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 0) + ctx.set(dut.pins[3].i, 0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) # - write 0xf to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 1) # - write 0x22 to SetClr (clear pins[0] and pins[2]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x22) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x44 to SetClr (set pins[1] and pins[3]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x44) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0xff to SetClr (no-op): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0xff) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # PUSH_PULL mode ====================================================================== # - write Mode: - yield from self._csr_access(dut, mode_addr, w_stb=1, w_data=0b01010101) - yield Tick() + await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b01010101) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.alt_mode[n]), 0) - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.alt_mode[n]), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - read Input: - yield dut.pins[1].i.eq(1) - yield dut.pins[3].i.eq(1) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield dut.pins[1].i.eq(0) - yield dut.pins[3].i.eq(0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0xa) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 1) + ctx.set(dut.pins[3].i, 1) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 0) + ctx.set(dut.pins[3].i, 0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) # - write 0xf to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 1) # - write 0x22 to SetClr (clear pins[0] and pins[2]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x22) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x44 to SetClr (set pins[1] and pins[3]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x44) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0xff to SetClr (no-op): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0xff) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # OPEN_DRAIN mode ===================================================================== # - write Mode: - yield from self._csr_access(dut, mode_addr, w_stb=1, w_data=0b10101010) - yield Tick() + await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b10101010) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.alt_mode[n]), 0) - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.alt_mode[n]), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - read Input: - yield dut.pins[1].i.eq(1) - yield dut.pins[3].i.eq(1) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield dut.pins[1].i.eq(0) - yield dut.pins[3].i.eq(0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0xa) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 1) + ctx.set(dut.pins[3].i, 1) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 0) + ctx.set(dut.pins[3].i, 0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) # - write 0xf to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x22 to SetClr (clear pins[0] and pins[2]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x22) - yield Tick() - self.assertEqual((yield dut.pins[0].oe), 1) - self.assertEqual((yield dut.pins[1].oe), 0) - self.assertEqual((yield dut.pins[2].oe), 1) - self.assertEqual((yield dut.pins[3].oe), 0) + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22) + await ctx.tick() + self.assertEqual(ctx.get(dut.pins[0].oe), 1) + self.assertEqual(ctx.get(dut.pins[1].oe), 0) + self.assertEqual(ctx.get(dut.pins[2].oe), 1) + self.assertEqual(ctx.get(dut.pins[3].oe), 0) for n in range(4): - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x44 to SetClr (set pins[1] and pins[3]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x44) - yield Tick() - self.assertEqual((yield dut.pins[0].oe), 1) - self.assertEqual((yield dut.pins[1].oe), 0) - self.assertEqual((yield dut.pins[2].oe), 1) - self.assertEqual((yield dut.pins[3].oe), 0) + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44) + await ctx.tick() + self.assertEqual(ctx.get(dut.pins[0].oe), 1) + self.assertEqual(ctx.get(dut.pins[1].oe), 0) + self.assertEqual(ctx.get(dut.pins[2].oe), 1) + self.assertEqual(ctx.get(dut.pins[3].oe), 0) for n in range(4): - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0xff to SetClr (no-op): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0xff) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 1) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 1) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # ALTERNATE mode ====================================================================== # - write Mode: - yield from self._csr_access(dut, mode_addr, w_stb=1, w_data=0b11111111) - yield Tick() + await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b11111111) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.alt_mode[n]), 1) - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.alt_mode[n]), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - read Input: - yield dut.pins[1].i.eq(1) - yield dut.pins[3].i.eq(1) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield dut.pins[1].i.eq(0) - yield dut.pins[3].i.eq(0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0xa) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 1) + ctx.set(dut.pins[3].i, 1) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 0) + ctx.set(dut.pins[3].i, 0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) # - write 0xf to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 1) # - write 0x22 to SetClr (clear pins[0] and pins[2]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x22) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0x44 to SetClr (set pins[1] and pins[3]): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0x44) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[0].o), 0) - self.assertEqual((yield dut.pins[1].o), 1) - self.assertEqual((yield dut.pins[2].o), 0) - self.assertEqual((yield dut.pins[3].o), 1) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[0].o), 0) + self.assertEqual(ctx.get(dut.pins[1].o), 1) + self.assertEqual(ctx.get(dut.pins[2].o), 0) + self.assertEqual(ctx.get(dut.pins[3].o), 1) # - write 0x0 to Output: - yield from self._csr_access(dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) - yield Tick() + await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) # - write 0xff to SetClr (no-op): - yield from self._csr_access(dut, setclr_addr, w_stb=1, w_data=0xff) - yield Tick() + await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff) + await ctx.tick() for n in range(4): - self.assertEqual((yield dut.pins[n].oe), 0) - self.assertEqual((yield dut.pins[n].o), 0) + self.assertEqual(ctx.get(dut.pins[n].oe), 0) + self.assertEqual(ctx.get(dut.pins[n].o), 0) sim = Simulator(dut) sim.add_clock(1e-6) @@ -337,14 +337,14 @@ def test_sim_without_input_sync(self): dut = gpio.Peripheral(pin_count=4, addr_width=2, data_width=8, input_stages=0) input_addr = 0x1 - def testbench(): - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) - yield dut.pins[1].i.eq(1) - yield dut.pins[3].i.eq(1) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0xa) - yield dut.pins[1].i.eq(0) - yield dut.pins[3].i.eq(0) - yield from self._csr_access(dut, input_addr, r_stb=1, r_data=0x0) + async def testbench(ctx): + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) + ctx.set(dut.pins[1].i, 1) + ctx.set(dut.pins[3].i, 1) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa) + ctx.set(dut.pins[1].i, 0) + ctx.set(dut.pins[3].i, 0) + await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0) sim = Simulator(dut) sim.add_clock(1e-6) diff --git a/tests/test_wishbone_bus.py b/tests/test_wishbone_bus.py index 9da371e..c27a159 100644 --- a/tests/test_wishbone_bus.py +++ b/tests/test_wishbone_bus.py @@ -236,53 +236,51 @@ def test_simple(self): sub_2.memory_map = MemoryMap(addr_width=16, data_width=8) dut.add(sub_2) - def sim_test(): - yield dut.bus.adr.eq(0x10400 >> 2) - yield dut.bus.cyc.eq(1) - yield dut.bus.stb.eq(1) - yield dut.bus.sel.eq(0b11) - yield dut.bus.dat_w.eq(0x12345678) - yield dut.bus.lock.eq(1) - yield dut.bus.cti.eq(wishbone.CycleType.INCR_BURST) - yield dut.bus.bte.eq(wishbone.BurstTypeExt.WRAP_4) - yield sub_1.ack.eq(1) - yield sub_1.dat_r.eq(0xabcdef01) - yield sub_2.dat_r.eq(0x5678abcd) - yield Delay(1e-6) - self.assertEqual((yield sub_1.adr), 0x400 >> 2) - self.assertEqual((yield sub_1.cyc), 1) - self.assertEqual((yield sub_2.cyc), 0) - self.assertEqual((yield sub_1.stb), 1) - self.assertEqual((yield sub_1.sel), 0b11) - self.assertEqual((yield sub_1.dat_w), 0x12345678) - self.assertEqual((yield dut.bus.ack), 1) - self.assertEqual((yield dut.bus.err), 0) - self.assertEqual((yield dut.bus.rty), 0) - self.assertEqual((yield dut.bus.dat_r), 0xabcdef01) - - yield dut.bus.adr.eq(0x20400 >> 2) - yield sub_1.ack.eq(0) - yield sub_2.err.eq(1) - yield sub_2.rty.eq(1) - yield sub_2.stall.eq(1) - yield Delay(1e-6) - self.assertEqual((yield sub_2.adr), 0x400 >> 2) - self.assertEqual((yield sub_1.cyc), 0) - self.assertEqual((yield sub_2.cyc), 1) - self.assertEqual((yield sub_1.stb), 1) - self.assertEqual((yield sub_1.sel), 0b11) - self.assertEqual((yield sub_1.dat_w), 0x12345678) - self.assertEqual((yield sub_2.lock), 1) - self.assertEqual((yield sub_2.cti), wishbone.CycleType.INCR_BURST.value) - self.assertEqual((yield sub_2.bte), wishbone.BurstTypeExt.WRAP_4.value) - self.assertEqual((yield dut.bus.ack), 0) - self.assertEqual((yield dut.bus.err), 1) - self.assertEqual((yield dut.bus.rty), 1) - self.assertEqual((yield dut.bus.stall), 1) - self.assertEqual((yield dut.bus.dat_r), 0x5678abcd) + async def testbench(ctx): + ctx.set(dut.bus.adr, 0x10400 >> 2) + ctx.set(dut.bus.cyc, 1) + ctx.set(dut.bus.stb, 1) + ctx.set(dut.bus.sel, 0b11) + ctx.set(dut.bus.dat_w, 0x12345678) + ctx.set(dut.bus.lock, 1) + ctx.set(dut.bus.cti, wishbone.CycleType.INCR_BURST) + ctx.set(dut.bus.bte, wishbone.BurstTypeExt.WRAP_4) + ctx.set(sub_1.ack, 1) + ctx.set(sub_1.dat_r, 0xabcdef01) + ctx.set(sub_2.dat_r, 0x5678abcd) + self.assertEqual(ctx.get(sub_1.adr), 0x400 >> 2) + self.assertEqual(ctx.get(sub_1.cyc), 1) + self.assertEqual(ctx.get(sub_2.cyc), 0) + self.assertEqual(ctx.get(sub_1.stb), 1) + self.assertEqual(ctx.get(sub_1.sel), 0b11) + self.assertEqual(ctx.get(sub_1.dat_w), 0x12345678) + self.assertEqual(ctx.get(dut.bus.ack), 1) + self.assertEqual(ctx.get(dut.bus.err), 0) + self.assertEqual(ctx.get(dut.bus.rty), 0) + self.assertEqual(ctx.get(dut.bus.dat_r), 0xabcdef01) + + ctx.set(dut.bus.adr, 0x20400 >> 2) + ctx.set(sub_1.ack, 0) + ctx.set(sub_2.err, 1) + ctx.set(sub_2.rty, 1) + ctx.set(sub_2.stall, 1) + self.assertEqual(ctx.get(sub_2.adr), 0x400 >> 2) + self.assertEqual(ctx.get(sub_1.cyc), 0) + self.assertEqual(ctx.get(sub_2.cyc), 1) + self.assertEqual(ctx.get(sub_1.stb), 1) + self.assertEqual(ctx.get(sub_1.sel), 0b11) + self.assertEqual(ctx.get(sub_1.dat_w), 0x12345678) + self.assertEqual(ctx.get(sub_2.lock), 1) + self.assertEqual(ctx.get(sub_2.cti), wishbone.CycleType.INCR_BURST.value) + self.assertEqual(ctx.get(sub_2.bte), wishbone.BurstTypeExt.WRAP_4.value) + self.assertEqual(ctx.get(dut.bus.ack), 0) + self.assertEqual(ctx.get(dut.bus.err), 1) + self.assertEqual(ctx.get(dut.bus.rty), 1) + self.assertEqual(ctx.get(dut.bus.stall), 1) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x5678abcd) sim = Simulator(dut) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -319,81 +317,71 @@ def elaborate(self, platform): self.assertEqual(dut.add(loop_4.bus, addr=0x40000, sparse=True), (0x40000, 0x40100, 1)) - def sim_test(): - yield dut.bus.cyc.eq(1) + async def testbench(ctx): + ctx.set(dut.bus.cyc, 1) + ctx.set(dut.bus.adr, 0x10010 >> 1) - yield dut.bus.adr.eq(0x10010 >> 1) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x00090008) - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x00090008) + ctx.set(dut.bus.sel, 0b01) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x00000008) - yield dut.bus.sel.eq(0b01) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x00000008) + ctx.set(dut.bus.sel, 0b10) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x00090000) - yield dut.bus.sel.eq(0b10) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x00090000) + ctx.set(dut.bus.adr, 0x20010 >> 1) - yield dut.bus.adr.eq(0x20010 >> 1) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x13121110) - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x13121110) + ctx.set(dut.bus.sel, 0b01) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x00001110) - yield dut.bus.sel.eq(0b01) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x00001110) + ctx.set(dut.bus.sel, 0b10) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x13120000) - yield dut.bus.sel.eq(0b10) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x13120000) + ctx.set(dut.bus.adr, 0x30010 >> 1) - yield dut.bus.adr.eq(0x30010 >> 1) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x0008) - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x0008) + ctx.set(dut.bus.sel, 0b01) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x0008) - yield dut.bus.sel.eq(0b01) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x0008) + ctx.set(dut.bus.sel, 0b10) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x0000) - yield dut.bus.sel.eq(0b10) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x0000) + ctx.set(dut.bus.adr, 0x30012 >> 1) - yield dut.bus.adr.eq(0x30012 >> 1) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x0009) - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x0009) + ctx.set(dut.bus.adr, 0x40010 >> 1) - yield dut.bus.adr.eq(0x40010 >> 1) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x08) - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x08) + ctx.set(dut.bus.sel, 0b01) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x08) - yield dut.bus.sel.eq(0b01) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x08) + ctx.set(dut.bus.sel, 0b10) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x00) - yield dut.bus.sel.eq(0b10) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x00) + ctx.set(dut.bus.adr, 0x40012 >> 1) - yield dut.bus.adr.eq(0x40012 >> 1) - - yield dut.bus.sel.eq(0b11) - yield Delay(1e-6) - self.assertEqual((yield dut.bus.dat_r), 0x09) + ctx.set(dut.bus.sel, 0b11) + self.assertEqual(ctx.get(dut.bus.dat_r), 0x09) m = Module() - m.submodules += dut, loop_1, loop_2, loop_3, loop_4 + m.submodules.loop_1 = loop_1 + m.submodules.loop_2 = loop_2 + m.submodules.loop_3 = loop_3 + m.submodules.loop_4 = loop_4 + m.submodules.dut = dut + sim = Simulator(m) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -403,19 +391,15 @@ def test_coarse_granularity(self): sub.memory_map = MemoryMap(addr_width=2, data_width=32) dut.add(sub) - def sim_test(): - yield dut.bus.cyc.eq(1) - - yield dut.bus.adr.eq(0x0) - yield Delay(1e-6) - self.assertEqual((yield sub.cyc), 1) - - yield dut.bus.adr.eq(0x4) - yield Delay(1e-6) - self.assertEqual((yield sub.cyc), 0) + async def testbench(ctx): + ctx.set(dut.bus.cyc, 1) + ctx.set(dut.bus.adr, 0x0) + self.assertEqual(ctx.get(sub.cyc), 1) + ctx.set(dut.bus.adr, 0x4) + self.assertEqual(ctx.get(sub.cyc), 0) sim = Simulator(dut) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -476,64 +460,62 @@ def test_simple(self): path=("intr_2",)) dut.add(intr_2) - def sim_test(): - yield intr_1.adr.eq(0x7ffffffc >> 2) - yield intr_1.cyc.eq(1) - yield intr_1.stb.eq(1) - yield intr_1.sel.eq(0b1111) - yield intr_1.we.eq(1) - yield intr_1.dat_w.eq(0x12345678) - yield dut.bus.dat_r.eq(0xabcdef01) - yield dut.bus.ack.eq(1) - yield dut.bus.err.eq(1) - yield dut.bus.rty.eq(1) - yield Delay(1e-7) - self.assertEqual((yield dut.bus.adr), 0x7ffffffc >> 2) - self.assertEqual((yield dut.bus.cyc), 1) - self.assertEqual((yield dut.bus.stb), 1) - self.assertEqual((yield dut.bus.sel), 0b1111) - self.assertEqual((yield dut.bus.we), 1) - self.assertEqual((yield dut.bus.dat_w), 0x12345678) - self.assertEqual((yield dut.bus.lock), 0) - self.assertEqual((yield dut.bus.cti), wishbone.CycleType.CLASSIC.value) - self.assertEqual((yield dut.bus.bte), wishbone.BurstTypeExt.LINEAR.value) - self.assertEqual((yield intr_1.dat_r), 0xabcdef01) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_1.err), 1) - self.assertEqual((yield intr_1.rty), 1) - - yield intr_1.cyc.eq(0) - yield intr_2.adr.eq(0xe0000000 >> 2) - yield intr_2.cyc.eq(1) - yield intr_2.stb.eq(1) - yield intr_2.sel.eq(0b10) - yield intr_2.we.eq(1) - yield intr_2.dat_w.eq(0x43218765) - yield intr_2.lock.eq(0) - yield intr_2.cti.eq(wishbone.CycleType.INCR_BURST) - yield intr_2.bte.eq(wishbone.BurstTypeExt.WRAP_4) - yield Tick() - - yield dut.bus.stall.eq(0) - yield Delay(1e-7) - self.assertEqual((yield dut.bus.adr), 0xe0000000 >> 2) - self.assertEqual((yield dut.bus.cyc), 1) - self.assertEqual((yield dut.bus.stb), 1) - self.assertEqual((yield dut.bus.sel), 0b1100) - self.assertEqual((yield dut.bus.we), 1) - self.assertEqual((yield dut.bus.dat_w), 0x43218765) - self.assertEqual((yield dut.bus.lock), 0) - self.assertEqual((yield dut.bus.cti), wishbone.CycleType.INCR_BURST.value) - self.assertEqual((yield dut.bus.bte), wishbone.BurstTypeExt.WRAP_4.value) - self.assertEqual((yield intr_2.dat_r), 0xabcdef01) - self.assertEqual((yield intr_2.ack), 1) - self.assertEqual((yield intr_2.err), 1) - self.assertEqual((yield intr_2.rty), 1) - self.assertEqual((yield intr_2.stall), 0) + async def testbench(ctx): + ctx.set(intr_1.adr, 0x7ffffffc >> 2) + ctx.set(intr_1.cyc, 1) + ctx.set(intr_1.stb, 1) + ctx.set(intr_1.sel, 0b1111) + ctx.set(intr_1.we, 1) + ctx.set(intr_1.dat_w, 0x12345678) + ctx.set(dut.bus.dat_r, 0xabcdef01) + ctx.set(dut.bus.ack, 1) + ctx.set(dut.bus.err, 1) + ctx.set(dut.bus.rty, 1) + self.assertEqual(ctx.get(dut.bus.adr), 0x7ffffffc >> 2) + self.assertEqual(ctx.get(dut.bus.cyc), 1) + self.assertEqual(ctx.get(dut.bus.stb), 1) + self.assertEqual(ctx.get(dut.bus.sel), 0b1111) + self.assertEqual(ctx.get(dut.bus.we), 1) + self.assertEqual(ctx.get(dut.bus.dat_w), 0x12345678) + self.assertEqual(ctx.get(dut.bus.lock), 0) + self.assertEqual(ctx.get(dut.bus.cti), wishbone.CycleType.CLASSIC.value) + self.assertEqual(ctx.get(dut.bus.bte), wishbone.BurstTypeExt.LINEAR.value) + self.assertEqual(ctx.get(intr_1.dat_r), 0xabcdef01) + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_1.err), 1) + self.assertEqual(ctx.get(intr_1.rty), 1) + + ctx.set(intr_1.cyc, 0) + ctx.set(intr_2.adr, 0xe0000000 >> 2) + ctx.set(intr_2.cyc, 1) + ctx.set(intr_2.stb, 1) + ctx.set(intr_2.sel, 0b10) + ctx.set(intr_2.we, 1) + ctx.set(intr_2.dat_w, 0x43218765) + ctx.set(intr_2.lock, 0) + ctx.set(intr_2.cti, wishbone.CycleType.INCR_BURST) + ctx.set(intr_2.bte, wishbone.BurstTypeExt.WRAP_4) + await ctx.tick() + + ctx.set(dut.bus.stall, 0) + self.assertEqual(ctx.get(dut.bus.adr), 0xe0000000 >> 2) + self.assertEqual(ctx.get(dut.bus.cyc), 1) + self.assertEqual(ctx.get(dut.bus.stb), 1) + self.assertEqual(ctx.get(dut.bus.sel), 0b1100) + self.assertEqual(ctx.get(dut.bus.we), 1) + self.assertEqual(ctx.get(dut.bus.dat_w), 0x43218765) + self.assertEqual(ctx.get(dut.bus.lock), 0) + self.assertEqual(ctx.get(dut.bus.cti), wishbone.CycleType.INCR_BURST.value) + self.assertEqual(ctx.get(dut.bus.bte), wishbone.BurstTypeExt.WRAP_4.value) + self.assertEqual(ctx.get(intr_2.dat_r), 0xabcdef01) + self.assertEqual(ctx.get(intr_2.ack), 1) + self.assertEqual(ctx.get(intr_2.err), 1) + self.assertEqual(ctx.get(intr_2.rty), 1) + self.assertEqual(ctx.get(intr_2.stall), 0) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -545,48 +527,42 @@ def test_lock(self): intr_2 = sig.create(path=("intr_2",)) dut.add(intr_2) - def sim_test(): - yield intr_1.cyc.eq(1) - yield intr_1.lock.eq(1) - yield intr_2.cyc.eq(1) - yield dut.bus.ack.eq(1) - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - - yield intr_1.lock.eq(0) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 0) - self.assertEqual((yield intr_2.ack), 1) - - yield intr_2.cyc.eq(0) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - - yield intr_1.stb.eq(1) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - - yield intr_1.stb.eq(0) - yield intr_2.cyc.eq(1) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 0) - self.assertEqual((yield intr_2.ack), 1) + async def testbench(ctx): + ctx.set(intr_1.cyc, 1) + ctx.set(intr_1.lock, 1) + ctx.set(intr_2.cyc, 1) + ctx.set(dut.bus.ack, 1) + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + + ctx.set(intr_1.lock, 0) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 0) + self.assertEqual(ctx.get(intr_2.ack), 1) + + ctx.set(intr_2.cyc, 0) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + + ctx.set(intr_1.stb, 1) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + + ctx.set(intr_1.stb, 0) + ctx.set(intr_2.cyc, 1) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 0) + self.assertEqual(ctx.get(intr_2.ack), 1) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -598,21 +574,19 @@ def test_stall(self): intr_2 = sig.create(path=("intr_2",)) dut.add(intr_2) - def sim_test(): - yield intr_1.cyc.eq(1) - yield intr_2.cyc.eq(1) - yield dut.bus.stall.eq(0) - yield Delay(1e-6) - self.assertEqual((yield intr_1.stall), 0) - self.assertEqual((yield intr_2.stall), 1) + async def testbench(ctx): + ctx.set(intr_1.cyc, 1) + ctx.set(intr_2.cyc, 1) + ctx.set(dut.bus.stall, 0) + self.assertEqual(ctx.get(intr_1.stall), 0) + self.assertEqual(ctx.get(intr_2.stall), 1) - yield dut.bus.stall.eq(1) - yield Delay(1e-6) - self.assertEqual((yield intr_1.stall), 1) - self.assertEqual((yield intr_2.stall), 1) + ctx.set(dut.bus.stall, 1) + self.assertEqual(ctx.get(intr_1.stall), 1) + self.assertEqual(ctx.get(intr_2.stall), 1) sim = Simulator(dut) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -624,20 +598,18 @@ def test_stall_compat(self): intr_2 = sig.create(path=("intr_2",)) dut.add(intr_2) - def sim_test(): - yield intr_1.cyc.eq(1) - yield intr_2.cyc.eq(1) - yield Delay(1e-6) - self.assertEqual((yield intr_1.stall), 1) - self.assertEqual((yield intr_2.stall), 1) + async def testbench(ctx): + ctx.set(intr_1.cyc, 1) + ctx.set(intr_2.cyc, 1) + self.assertEqual(ctx.get(intr_1.stall), 1) + self.assertEqual(ctx.get(intr_2.stall), 1) - yield dut.bus.ack.eq(1) - yield Delay(1e-6) - self.assertEqual((yield intr_1.stall), 0) - self.assertEqual((yield intr_2.stall), 1) + ctx.set(dut.bus.ack, 1) + self.assertEqual(ctx.get(intr_1.stall), 0) + self.assertEqual(ctx.get(intr_2.stall), 1) sim = Simulator(dut) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run() @@ -651,54 +623,49 @@ def test_roundrobin(self): intr_3 = sig.create(path=("intr_3",)) dut.add(intr_3) - def sim_test(): - yield intr_1.cyc.eq(1) - yield intr_2.cyc.eq(0) - yield intr_3.cyc.eq(1) - yield dut.bus.ack.eq(1) - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - self.assertEqual((yield intr_3.ack), 0) - - yield intr_1.cyc.eq(0) - yield intr_2.cyc.eq(0) - yield intr_3.cyc.eq(1) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 0) - self.assertEqual((yield intr_2.ack), 0) - self.assertEqual((yield intr_3.ack), 1) - - yield intr_1.cyc.eq(1) - yield intr_2.cyc.eq(1) - yield intr_3.cyc.eq(0) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 1) - self.assertEqual((yield intr_2.ack), 0) - self.assertEqual((yield intr_3.ack), 0) - - yield intr_1.cyc.eq(0) - yield intr_2.cyc.eq(1) - yield intr_3.cyc.eq(1) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 0) - self.assertEqual((yield intr_2.ack), 1) - self.assertEqual((yield intr_3.ack), 0) - - yield intr_1.cyc.eq(1) - yield intr_2.cyc.eq(0) - yield intr_3.cyc.eq(1) - yield Tick() - yield Delay(1e-7) - self.assertEqual((yield intr_1.ack), 0) - self.assertEqual((yield intr_2.ack), 0) - self.assertEqual((yield intr_3.ack), 1) + async def testbench(ctx): + ctx.set(intr_1.cyc, 1) + ctx.set(intr_2.cyc, 0) + ctx.set(intr_3.cyc, 1) + ctx.set(dut.bus.ack, 1) + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + self.assertEqual(ctx.get(intr_3.ack), 0) + + ctx.set(intr_1.cyc, 0) + ctx.set(intr_2.cyc, 0) + ctx.set(intr_3.cyc, 1) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 0) + self.assertEqual(ctx.get(intr_2.ack), 0) + self.assertEqual(ctx.get(intr_3.ack), 1) + + ctx.set(intr_1.cyc, 1) + ctx.set(intr_2.cyc, 1) + ctx.set(intr_3.cyc, 0) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 1) + self.assertEqual(ctx.get(intr_2.ack), 0) + self.assertEqual(ctx.get(intr_3.ack), 0) + + ctx.set(intr_1.cyc, 0) + ctx.set(intr_2.cyc, 1) + ctx.set(intr_3.cyc, 1) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 0) + self.assertEqual(ctx.get(intr_2.ack), 1) + self.assertEqual(ctx.get(intr_3.ack), 0) + + ctx.set(intr_1.cyc, 1) + ctx.set(intr_2.cyc, 0) + ctx.set(intr_3.cyc, 1) + await ctx.tick() + self.assertEqual(ctx.get(intr_1.ack), 0) + self.assertEqual(ctx.get(intr_2.ack), 0) + self.assertEqual(ctx.get(intr_3.ack), 1) sim = Simulator(dut) sim.add_clock(1e-6) - sim.add_testbench(sim_test) + sim.add_testbench(testbench) with sim.write_vcd(vcd_file="test.vcd"): sim.run()