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Wishbone-attached SRAM #89
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Performance-wise, it would also benefit from Wishbone incremental bursts. This implementation could be useful as a starting point. |
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It would be nice to have a Wishbone-attached SRAM peripheral, to enable CPU cores to have scratchpad RAM.
Since there is an ambiguity about what to do for non-power-of-2 sizes of such RAM, I propose that they be prohibited. There is some usefulness but it's unclear what to do on out-of-bounds accesses (wrap? set
err
? if you seterr
when do you clear it?) so it's probably best to punt on this.The text was updated successfully, but these errors were encountered: