diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 266580f..d79c104 100644
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -208,8 +208,9 @@ def sim_test():
             yield Delay(1e-6)
             self.assertEqual((yield sub_1.adr), 0x400 >> 2)
             self.assertEqual((yield sub_1.cyc), 1)
-            self.assertEqual((yield sub_2.cyc), 0)
             self.assertEqual((yield sub_1.stb), 1)
+            self.assertEqual((yield sub_2.cyc), 0)
+            self.assertEqual((yield sub_2.stb), 0)
             self.assertEqual((yield sub_1.sel), 0b11)
             self.assertEqual((yield sub_1.dat_w), 0x12345678)
             self.assertEqual((yield dut.bus.ack), 1)
@@ -225,8 +226,9 @@ def sim_test():
             yield Delay(1e-6)
             self.assertEqual((yield sub_2.adr), 0x400 >> 2)
             self.assertEqual((yield sub_1.cyc), 0)
+            self.assertEqual((yield sub_1.stb), 0)
             self.assertEqual((yield sub_2.cyc), 1)
-            self.assertEqual((yield sub_1.stb), 1)
+            self.assertEqual((yield sub_2.stb), 1)
             self.assertEqual((yield sub_1.sel), 0b11)
             self.assertEqual((yield sub_1.dat_w), 0x12345678)
             self.assertEqual((yield sub_2.lock), 1)
diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py
index a62949b..b1a6fce 100644
--- a/nmigen_soc/wishbone/bus.py
+++ b/nmigen_soc/wishbone/bus.py
@@ -283,7 +283,6 @@ def elaborate(self, platform):
                     sub_bus.dat_w.eq(self.bus.dat_w),
                     sub_bus.sel.eq(Cat(Repl(sel, sub_ratio) for sel in self.bus.sel)),
                     sub_bus.we.eq(self.bus.we),
-                    sub_bus.stb.eq(self.bus.stb),
                 ]
                 if hasattr(sub_bus, "lock"):
                     m.d.comb += sub_bus.lock.eq(getattr(self.bus, "lock", 0))
@@ -295,6 +294,7 @@ def elaborate(self, platform):
                 granularity_bits = log2_int(self.bus.data_width // self.bus.granularity)
                 with m.Case(sub_pat[:-granularity_bits if granularity_bits > 0 else None]):
                     m.d.comb += [
+                        sub_bus.stb.eq(self.bus.stb),
                         sub_bus.cyc.eq(self.bus.cyc),
                         self.bus.dat_r.eq(sub_bus.dat_r),
                     ]