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Update Zephyr MSDK Hal based on MSDK PR: analogdevicesinc/msdk#1071
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5 files changed

+11
-11
lines changed

5 files changed

+11
-11
lines changed

MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -68,17 +68,17 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg)
6868
unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
6969
{
7070
// Figure 4-1 of the preliminary AI85 UG (04/01/2022) shows the SDHC hardware block
71-
// connected directly to the SYS_CLK node. This is most likely inaccurate, but the
71+
// connected directly to the IPO Clock node. This is most likely inaccurate, but the
7272
// register description for MXC_GCR->pclkdiv marks the usual SDHC divider as reserved.
7373
// We will follow figure 4-1 for now.
7474

7575
if (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIS1_SDHC) {
76-
return SystemCoreClock >> 2; // Div by 4
76+
return IPO_FREQ >> 2; // Div by 4
7777
} else {
78-
return SystemCoreClock >> 1; // Div by 2
78+
return IPO_FREQ >> 1; // Div by 2
7979
}
8080

81-
return SystemCoreClock;
81+
return IPO_FREQ;
8282
}
8383

8484
/* ************************************************************************** */

MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -85,9 +85,9 @@ unsigned int MXC_SDHC_Get_Clock_Config(void)
8585
unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
8686
{
8787
if (MXC_GCR->pclk_div & MXC_F_GCR_PCLK_DIV_SDHCFRQ) {
88-
return SystemCoreClock >> 1; // Div by 2
88+
return HIRC96_FREQ >> 1; // Div by 2
8989
} else {
90-
return 50000000; // UG specifies a hard-coded 50Mhz value in this case
90+
return 50000000; // UG specifies a hard-coded 50Mhz low-power oscillator
9191
}
9292
}
9393

MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,9 @@ unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
6868
{
6969
// TODO(JC): Confirm this is the scheme used by ME13
7070
if (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIV_SDHCFRQ) {
71-
return SystemCoreClock >> 2; // Div by 4
71+
return IPO_FREQ >> 2; // Div by 4
7272
} else {
73-
return SystemCoreClock >> 1; // Div by 2
73+
return IPO_FREQ >> 1; // Div by 2
7474
}
7575
}
7676

MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,9 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg)
6868
unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
6969
{
7070
if (MXC_GCR->pckdiv & MXC_F_GCR_PCKDIV_SDHCFRQ) {
71-
return SystemCoreClock >> 2; // Div by 4
71+
return HIRC96_FREQ >> 2; // Div by 4
7272
} else {
73-
return SystemCoreClock >> 1; // Div by 2
73+
return HIRC96_FREQ >> 1; // Div by 2
7474
}
7575
}
7676

MAX/msdk_sha

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
6ff04ecf174ebdd7c78a187034b483d180bba283
1+
4d53dd087b18b3d3bae5e17e6a5aef2f72077880

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