From 500b3fe6c2fb621abde2cbb7a91f231fbcb9bec7 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Fri, 13 Dec 2024 17:24:46 +0200 Subject: [PATCH] projets: Remove obsolete project ad_fmclidar1_ebz * Remove from CODEOWNERS as well Signed-off-by: Iulia Moldovan --- .github/CODEOWNERS | 3 - projects/ad_fmclidar1_ebz/Makefile | 7 - projects/ad_fmclidar1_ebz/Readme.md | 158 -------- projects/ad_fmclidar1_ebz/a10soc/Makefile | 25 -- .../ad_fmclidar1_ebz/a10soc/system_constr.sdc | 25 -- .../a10soc/system_project.tcl | 216 ---------- .../ad_fmclidar1_ebz/a10soc/system_qsys.tcl | 41 -- projects/ad_fmclidar1_ebz/a10soc/system_top.v | 374 ------------------ .../common/ad_fmclidar1_ebz_bd.tcl | 211 ---------- .../common/ad_fmclidar1_ebz_qsys.tcl | 236 ----------- .../common/util_axis_syncgen.v | 94 ----- .../ad_fmclidar1_ebz/common/util_tia_chsel.v | 63 --- .../ad_fmclidar1_ebz/doc/img/hdl_lidar.png | Bin 84019 -> 0 bytes projects/ad_fmclidar1_ebz/zc706/Makefile | 33 -- projects/ad_fmclidar1_ebz/zc706/system_bd.tcl | 57 --- .../ad_fmclidar1_ebz/zc706/system_constr.xdc | 110 ------ .../ad_fmclidar1_ebz/zc706/system_project.tcl | 17 - projects/ad_fmclidar1_ebz/zc706/system_top.v | 304 -------------- projects/ad_fmclidar1_ebz/zcu102/Makefile | 30 -- .../ad_fmclidar1_ebz/zcu102/system_bd.tcl | 59 --- .../ad_fmclidar1_ebz/zcu102/system_constr.xdc | 109 ----- .../zcu102/system_project.tcl | 17 - projects/ad_fmclidar1_ebz/zcu102/system_top.v | 234 ----------- 23 files changed, 2423 deletions(-) delete mode 100644 projects/ad_fmclidar1_ebz/Makefile delete mode 100644 projects/ad_fmclidar1_ebz/Readme.md delete mode 100644 projects/ad_fmclidar1_ebz/a10soc/Makefile delete mode 100644 projects/ad_fmclidar1_ebz/a10soc/system_constr.sdc delete mode 100644 projects/ad_fmclidar1_ebz/a10soc/system_project.tcl delete mode 100644 projects/ad_fmclidar1_ebz/a10soc/system_qsys.tcl delete mode 100644 projects/ad_fmclidar1_ebz/a10soc/system_top.v delete mode 100644 projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl delete mode 100644 projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_qsys.tcl delete mode 100644 projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v delete mode 100644 projects/ad_fmclidar1_ebz/common/util_tia_chsel.v delete mode 100644 projects/ad_fmclidar1_ebz/doc/img/hdl_lidar.png delete mode 100644 projects/ad_fmclidar1_ebz/zc706/Makefile delete mode 100644 projects/ad_fmclidar1_ebz/zc706/system_bd.tcl delete mode 100644 projects/ad_fmclidar1_ebz/zc706/system_constr.xdc delete mode 100644 projects/ad_fmclidar1_ebz/zc706/system_project.tcl delete mode 100644 projects/ad_fmclidar1_ebz/zc706/system_top.v delete mode 100644 projects/ad_fmclidar1_ebz/zcu102/Makefile delete mode 100644 projects/ad_fmclidar1_ebz/zcu102/system_bd.tcl delete mode 100644 projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc delete mode 100644 projects/ad_fmclidar1_ebz/zcu102/system_project.tcl delete mode 100644 projects/ad_fmclidar1_ebz/zcu102/system_top.v diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index a5ebc615762..aee9f0f0afd 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -115,9 +115,6 @@ # Code owners for ad9783_ebz folder /projects/ad9783_ebz/ iulia.moldovan@analog.com cristianmihai.popa@analog.com -# Code owners for ad_fmclidar1_ebz folder -/projects/ad_fmclidar1_ebz/ adrian.costina@analog.com andrei.grozav@analog.com - # Code owners for ad_quadmxfe1_ebz folder /projects/ad_quadmxfe1_ebz/ filip.gherman@analog.com iulia.moldovan@analog.com laez.barbosa@analog.com diff --git a/projects/ad_fmclidar1_ebz/Makefile b/projects/ad_fmclidar1_ebz/Makefile deleted file mode 100644 index 1402069e104..00000000000 --- a/projects/ad_fmclidar1_ebz/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -include ../scripts/project-toplevel.mk diff --git a/projects/ad_fmclidar1_ebz/Readme.md b/projects/ad_fmclidar1_ebz/Readme.md deleted file mode 100644 index 9d2a891f4aa..00000000000 --- a/projects/ad_fmclidar1_ebz/Readme.md +++ /dev/null @@ -1,158 +0,0 @@ - -# AD_FMCLIDAR1_EBZ HDL reference design - -## Overview - -The following design supports both Xilinx and Intel FPGA's. The [AD_FMCLIDAR1_EBZ](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCLIDAR1-EBZ.html) -prototyping system connects to the FPGA carrier board through a FMC (FPGA Mezzanine Cad) -high pin count connector. - -Detailed user guide of the prototyping platform can be found [here](https://wiki.analog.com/resources/eval/user-guides/ad-fmclidar1-ebz). - -Currently supported carriers: - -| Carrier name | FMC connector | -| ------------- | ------------- | -| ZC706 | FMC_HPC | -| ZCU102 | HPC0 | -| Arria10SOC* | FMCA_HPC | - -The design is easily portable to any Xilinx or Intel FPGA carrier board, which -has an FMC HPC connector, and have all the required connections. (See more info -in [system_constr.xdc](./zc706/system_constr.xdc) or [system_project.tcl](./a10soc/system_project.tcl)) - -You can find a porting guide in the [wiki.analog.com](https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide). - -### NOTE - -The Arria10SOC carrier requires a hardware rework to function correctly. -The rework connects FMC_A header pins directly to the FPGA so that they can be -accessed by the fabric. - -#### Changes required: - -**REMOVE**: R575, R576, R621, R633, R612, R613 - -**POPULATE**: R574, R577, R620, R632, R610, R611 - - -### Directory Structure - -| Directory | Description | -| --------- | ----------- | -| common | Common verilog and block design Tcl files | -| zc706 | ZC706 specific source files | -| zcu102 | ZCU102 specific source files | -| a10soc | Arria10SOC specific source files | - -More information about the directory structure of the HDL repository can be found [here](https://wiki.analog.com/resources/fpga/docs/git). - -## Build instructions - -The project is using GNU Make for build and bitstream generation. Change your directory -to your targeted carrier and run **make**. - -More information about how to build HDL projects can be found [here](http://wiki.analog.com/resources/fpga/docs/build). - -## Architecture - -The main scope of the HDL design is to provide all the required digital interfaces -for the data acquisition board of the prototyping system. - -The following block diagram presents the simplified system architecture: - -![HDL Block Diagram](./doc/img/hdl_lidar.png) - -### AXI_LASER_DRIVER IP - -The axi_laser_driver IP is responsible to generate a narrow pulse for the laser -driver circuit, to control the TIA channel selection on the analog front end (AFE) -board, and to synchronize the data acquisition to the generated pulses. - -More information about the IP can be found [here](https://wiki.analog.com/resources/fpga/docs/axi_laser_driver). - -### Control interfaces - -| Name | Type | Details | -| ---- | ---- | ------- | -| adc_fd* | GPIO | Monitors the AD9094 Fast detect output lines | -| adc_pwdn | GPIO | Controls the AD9094 Power-Down input line | -| spi_adc_* | 4-wire SPI | AD9094 configuration interface | -| spi_vco_* | 3-wire SPI | ADF436-7 configuration interface | -| spi_clkgen_* | 4-wire SPI | AD9528 configuration interface | -| laser_driver_p\n | LVDS output | It controls the laser driver circuit, it is generated by the axi_laser_driver IP instance | -| laser_gpio[13:0] | GPIO | Unused GPIO line on the lase board | -| tia_chsel[7:0] | CMOS output | TIA channel selection lines, it is controlled by the axi_laser_driver instance | -| afe_dac_sda\scl\load\clr_n | I2C/GPIO | AD5627 configuration interface | -| rx_ref_clk_p\n | LVDS | JESD204B reference clock for the high-speed gigabit transceivers; runs at 250MHz | -| rx_device_clk_p\n | LVDS | JESD204B device clock for the transport layer and additional data processing; runs at 250MHz | -| rx_data_p\n[3:0] | CML | JESD204B high-speed serial lanes; runs at 10Gbps | -| rx_sync_p\n[1:0] | LVDS | JESD204B SYNC signals for interface synchronization | -| rx_sysref_p\n | LVDS | JESD204B SYSREF signal for deterministic latency | - -### JESD204B interface - -The JESD204B interface runs in Subclass 1 mode to ensure the deterministic latency -of the link. The following tables are summarizing the JESD204B important configuration -parameter and attributes. - -| Parameter name | Abbreviation |Value | -| -------------- | ------------ | ---- | -| Number of lanes | L | 4 | -| Number of converter | M | 4 | -| Converter resolution | NP | 8 | -| Total number of Bits per Sample| NP | 8 | -| Samples per frame | S | 1 | -| Octets per frame | F | 1 | -| Frames per Multiframe | K | 32 | -| Number of control bits | CS | 0 | - -| Rates and Clocks | Value | -| ---------------- | ----- | -| Sample rate | 1GSPS | -| Lane rate | 10Gbps | -| GT reference clock | 250MHz | -| Device clock | 250 MHz | - -## Known issues - -### The Lidar boards do not power up - -**Problem:** The Lidar boards do not power up because the PG_C2M pull-up resistor value on the carrier (Arria 10) is too high. - -**Solution:** On Arria 10 - place a 4k7 ohms resistor in parallel with R5517. - -**Note:** - -1. The PG_C2M can no longer be software controlled. As soon as there is an auxiliary 3V3 on the carrier, the Lidar platform receives the power up command. -2. This problem only affects Lidar Rev B. - -## Support - -For technical support please visit [FPGA Referece Designs](https://ez.analog.com/fpga/) community in EngineerZone. - - -# AD_FMCLIDAR1_EBZ HDL Project - -Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/AD-FMCLIDAR1-EBZ) - * Parts : - * Laser Board - [3.3 V, 200 Mbps, Half-Duplex, High Speed M-LVDS Transceiver with Type 1 Receiver](https://www.analog.com/adn4691e) - [High Speed, Dual, 4 A MOSFET Driver, non-inverting A/B input pins, 9.5V < VIN < 18V](https://www.analog.com/adp3634) - [Ultralow Noise Drivers for Low Voltage ADCs](https://www.analog.com/ada4930-1) - * DAQ Board - [8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter](https://www.analog.com/ad9094) - [Integrated Synthesizer and VCO](https://www.analog.com/adf4360-7) - [JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs](https://www.analog.com/ad9528) - [1.2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator](https://www.analog.com/adp7156) - [2 A, Ultralow Noise, High PSRR, Adjustable Output, RF Linear Regulator](https://www.analog.com/adp7159) - * AFE Board - [Four-Channel Multiplexed Transimpedance Amplifier with Output Multiplexing](https://www.analog.com/ltc6561) - [Low Power Selectable Gain Differential ADC Driver](https://www.analog.com/ada4950-1) - [Dual 3.2MHz, 0.8V/μs Low Power, Over-The-Top Precision Op Amp](https://www.analog.com/lt6016) - [Micropower, Precision, Auto Qualified 2.5V Voltage Reference](https://www.analog.com/adr3525) - [Low IQ Boost/SEPIC/Flyback/Inverting Converter with 0.5A, 140V Switch](https://www.analog.com/lt8331) - * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmclidar1-ebz - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmclidar1-ebz - * Linux Drivers: https://wiki.analog.com/resources/fpga/docs/axi_laser_driver diff --git a/projects/ad_fmclidar1_ebz/a10soc/Makefile b/projects/ad_fmclidar1_ebz/a10soc/Makefile deleted file mode 100644 index 1a1e6f537c5..00000000000 --- a/projects/ad_fmclidar1_ebz/a10soc/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := ad_fmclidar1_ebz_a10soc - -M_DEPS += ../common/ad_fmclidar1_ebz_qsys.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl -M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl -M_DEPS += ../../ad_fmclidar1_ebz/common/util_tia_chsel.v -M_DEPS += ../../ad_fmclidar1_ebz/common/util_axis_syncgen.v -M_DEPS += ../../../library/util_cdc/sync_bits.v - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_laser_driver -LIB_DEPS += axi_sysid -LIB_DEPS += intel/adi_jesd204 -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 - -include ../../scripts/project-intel.mk diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_constr.sdc b/projects/ad_fmclidar1_ebz/a10soc/system_constr.sdc deleted file mode 100644 index 53ab0f99399..00000000000 --- a/projects/ad_fmclidar1_ebz/a10soc/system_constr.sdc +++ /dev/null @@ -1,25 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "4.000 ns" -name rx_device_clk [get_ports {rx_device_clk}] -create_clock -period "4.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}] - -# Asynchronous GPIOs - -foreach async_input {adc_fda adc_fdb gpio_bd_i[*]} { - set_false_path -from [get_ports $async_input] -} - -foreach async_output {laser_gpio[*] afe_adc_convst afe_dac_load afe_dac_clr_n adc_pdwn gpio_bd_o[*]} { - set_false_path -to [get_ports $async_output] -} - -derive_pll_clocks -derive_clock_uncertainty - -set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -to [get_registers *i_util_axis_syncgen*i_axis_ext_sync|cdc_sync_stage1*] - diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl b/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl deleted file mode 100644 index 9141f2b5fe3..00000000000 --- a/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl +++ /dev/null @@ -1,216 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source ../../scripts/adi_project_intel.tcl - -adi_project ad_fmclidar1_ebz_a10soc - -source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl - -# files - -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/util_cdc/sync_bits.v - -# -# Note: This project requires a hardware rework to function correctly. -# The rework connects FMC_A header pins directly to the FPGA so that they can be -# accessed by the fabric. -# -# Changes required: -# -# REMOVE: R575, R576, R621, R633, R612, R613 -# -# POPULATE: R574, R577, R620, R632, R610, R611 -# - -# ADC digital interface (JESD204B) - -set_location_assignment PIN_N29 -to rx_ref_clk ; ## D04 FMCA_HPC_GBTCLK0_M2C_P -set_location_assignment PIN_N28 -to "rx_ref_clk(n)" ; ## D05 FMCA_HPC_GBTCLK0_M2C_N - -## NOTE: Need hardware rework -set_location_assignment PIN_W5 -to rx_device_clk ; ## G02 FMCA_HPC_CLK1_M2C_P -set_location_assignment PIN_W6 -to "rx_device_clk(n)" ; ## G03 FMCA_HPC_CLK1_M2C_N - -set_location_assignment PIN_T31 -to rx_data[0] ; ## C06 FMCA_HPC_DP00_M2C_P -set_location_assignment PIN_T30 -to "rx_data[0](n)" ; ## C07 FMCA_HPC_DP00_M2C_N -set_location_assignment PIN_R33 -to rx_data[1] ; ## A02 FMCA_HPC_DP01_M2C_P -set_location_assignment PIN_R32 -to "rx_data[1](n)" ; ## A03 FMCA_HPC_DP01_M2C_N -set_location_assignment PIN_P35 -to rx_data[2] ; ## A06 FMCA_HPC_DP02_M2C_P -set_location_assignment PIN_P34 -to "rx_data[2](n)" ; ## A07 FMCA_HPC_DP02_M2C_N -set_location_assignment PIN_P31 -to rx_data[3] ; ## A10 FMCA_HPC_DP03_M2C_P -set_location_assignment PIN_P30 -to "rx_data[3](n)" ; ## A11 FMCA_HPC_DP03_M2C_N - -set_location_assignment PIN_A9 -to rx_sync_0 ; ## H13 FMCA_HPC_LA07_P -set_location_assignment PIN_B9 -to "rx_sync_0(n)" ; ## H14 FMCA_HPC_LA07_N -set_location_assignment PIN_H12 -to rx_sync_1 ; ## H10 FMCA_HPC_LA04_P -set_location_assignment PIN_H13 -to "rx_sync_1(n)" ; ## H11 FMCA_HPC_LA04_N - -## NOTE: Need hardware rework -set_location_assignment PIN_E12 -to rx_sysref ; ## D08 FMCA_HPC_LA01_CC_P -set_location_assignment PIN_E13 -to "rx_sysref(n)" ; ## D09 FMCA_HPC_LA01_CC_N - -set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_clk -set_instance_assignment -name IO_STANDARD LVDS -to "rx_ref_clk(n)" -set_instance_assignment -name IO_STANDARD LVDS -to rx_device_clk -set_instance_assignment -name IO_STANDARD LVDS -to "rx_device_clk(n)" -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_0 -set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync_0(n)" -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_1 -set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync_1(n)" -set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref -set_instance_assignment -name IO_STANDARD LVDS -to "rx_sysref(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sync_0 -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "rx_sync_0(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sync_1 -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "rx_sync_1(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "rx_sysref(n)" - -# ADC control lines - -set_location_assignment PIN_D13 -to adc_pdwn ; ## H08 FMCA_HPC_LA02_N -set_location_assignment PIN_C14 -to adc_fda ; ## G09 FMCA_HPC_LA03_P -set_location_assignment PIN_D14 -to adc_fdb ; ## G10 FMCA_HPC_LA03_N - -set_instance_assignment -name IO_STANDARD "1.8V" -to adc_pdwn -set_instance_assignment -name IO_STANDARD "1.8V" -to adc_fda -set_instance_assignment -name IO_STANDARD "1.8V" -to adc_fdb - -# SPI interfaces - -set_location_assignment PIN_A10 -to spi_adc_csn ; ## C10 FMCA_HPC_LA06_P -set_location_assignment PIN_P11 -to spi_adc_clk ; ## G36 FMCA_HPC_LA33_P -set_location_assignment PIN_C13 -to spi_adc_miso ; ## H07 FMCA_HPC_LA02_P -set_location_assignment PIN_R11 -to spi_adc_mosi ; ## G37 FMCA_HPC_LA33_N - -set_location_assignment PIN_D4 -to spi_vco_csn ; ## H19 FMCA_HPC_LA15_P -set_location_assignment PIN_C9 -to spi_vco_clk ; ## H16 FMCA_HPC_LA11_P -set_location_assignment PIN_D9 -to spi_vco_mosi ; ## H17 FMCA_HPC_LA11_N - -set_location_assignment PIN_C2 -to spi_clkgen_csn ; ## H25 FMCA_HPC_LA21_P -set_location_assignment PIN_G5 -to spi_clkgen_clk ; ## H22 FMCA_HPC_LA19_P -set_location_assignment PIN_D3 -to spi_clkgen_miso ; ## H26 FMCA_HPC_LA21_N -set_location_assignment PIN_G6 -to spi_clkgen_mosi ; ## H23 FMCA_HPC_LA19_N - -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_adc_csn -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_adc_clk -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_adc_miso -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_adc_mosi - -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_vco_csn -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_vco_clk -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_vco_mosi - -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clkgen_csn -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clkgen_clk -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clkgen_miso -set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clkgen_mosi - -# Laser driver and GPIOs - -set_location_assignment PIN_G7 -to laser_driver ; ## C22 FMCA_HPC_LA18_CC_P -set_location_assignment PIN_H7 -to "laser_driver(n)" ; ## C23 FMCA_HPC_LA18_CC_N - -set_location_assignment PIN_G1 -to laser_driver_en_n ; ## C26 FMCA_HPC_LA27_P -set_location_assignment PIN_P8 -to laser_driver_otw_n ; ## G33 FMCA_HPC_LA31_P - -set_location_assignment PIN_H2 -to laser_gpio[0] ; ## C27 FMCA_HPC_LA27_N -set_location_assignment PIN_F9 -to laser_gpio[1] ; ## D20 FMCA_HPC_LA17_CC_P -set_location_assignment PIN_G9 -to laser_gpio[2] ; ## D21 FMCA_HPC_LA17_CC_N -set_location_assignment PIN_C1 -to laser_gpio[3] ; ## D23 FMCA_HPC_LA23_P -set_location_assignment PIN_D1 -to laser_gpio[4] ; ## D24 FMCA_HPC_LA23_N -set_location_assignment PIN_F2 -to laser_gpio[5] ; ## D26 FMCA_HPC_LA26_P -set_location_assignment PIN_G2 -to laser_gpio[6] ; ## D27 FMCA_HPC_LA26_N -set_location_assignment PIN_F4 -to laser_gpio[7] ; ## G24 FMCA_HPC_LA22_P -set_location_assignment PIN_G4 -to laser_gpio[8] ; ## G25 FMCA_HPC_LA22_N -set_location_assignment PIN_E3 -to laser_gpio[9] ; ## G27 FMCA_HPC_LA25_P -set_location_assignment PIN_F3 -to laser_gpio[10] ; ## G28 FMCA_HPC_LA25_N -set_location_assignment PIN_N9 -to laser_gpio[11] ; ## G30 FMCA_HPC_LA29_P -set_location_assignment PIN_P10 -to laser_gpio[12] ; ## G31 FMCA_HPC_LA29_N -set_location_assignment PIN_R8 -to laser_gpio[13] ; ## G34 FMCA_HPC_LA31_N - -set_instance_assignment -name IO_STANDARD LVDS -to laser_driver -set_instance_assignment -name IO_STANDARD LVDS -to "laser_driver(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to laser_driver -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "laser_driver(n)" - -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_driver_en_n -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_driver_otw_n - -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[0] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[1] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[2] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[3] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[4] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[5] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[6] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[7] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[8] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[9] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[10] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[11] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[12] -set_instance_assignment -name IO_STANDARD "1.8V" -to laser_gpio[13] - -# TIA channel selection - -set_location_assignment PIN_B10 -to tia_chsel[0] ; ## afe_sel0_1 C11 FMCA_HPC_LA06_N -set_location_assignment PIN_A7 -to tia_chsel[1] ; ## afe_sel1_1 C14 FMCA_HPC_LA10_P -set_location_assignment PIN_A8 -to tia_chsel[2] ; ## afe_sel0_2 C15 FMCA_HPC_LA10_N -set_location_assignment PIN_J9 -to tia_chsel[3] ; ## afe_sel1_2 C18 FMCA_HPC_LA14_P -set_location_assignment PIN_J10 -to tia_chsel[4] ; ## afe_sel0_3 C19 FMCA_HPC_LA14_N - -## NOTE: Need hardware rework -set_location_assignment PIN_F13 -to tia_chsel[5] ; ## afe_sel1_3 D11 FMCB_HPC_LA05_P -set_location_assignment PIN_F14 -to tia_chsel[6] ; ## afe_sel0_4 D12 FMCA_HPC_LA05_N - -set_location_assignment PIN_A12 -to tia_chsel[7] ; ## afe_sel1_4 D14 FMCA_HPC_LA09_P - -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[0] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[1] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[2] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[3] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[4] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[5] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[6] -set_instance_assignment -name IO_STANDARD "1.8V" -to tia_chsel[7] - -# AFE DAC I2C and control - -set_location_assignment PIN_A13 -to afe_dac_sda ; ## D15 FMCA_HPC_LA09_N -set_location_assignment PIN_J11 -to afe_dac_scl ; ## D17 FMCA_HPC_LA13_P -set_location_assignment PIN_K11 -to afe_dac_clr_n ; ## D18 FMCA_HPC_LA13_N -set_location_assignment PIN_G14 -to afe_dac_load ; ## G06 FMCA_HPC_LA00_CC_P - -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_dac_sda -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_dac_scl -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_dac_clr_n -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_dac_load - -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to afe_dac_scl -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to afe_dac_sda - -# AFE ADC SPI and control - -set_location_assignment PIN_H14 -to afe_adc_sclk ; ## G07 FMCA_HPC_LA00_CC_N -set_location_assignment PIN_B11 -to afe_adc_scn ; ## G12 FMCA_HPC_LA08_P -set_location_assignment PIN_B12 -to afe_adc_convst ; ## G13 FMCA_HPC_LA08_N -set_location_assignment PIN_M12 -to afe_adc_sdi ; ## G15 FMCA_HPC_LA12_P - -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_adc_sclk -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_adc_scn -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_adc_convst -set_instance_assignment -name IO_STANDARD "1.8V" -to afe_adc_sdi - -# set optimization to get a better timing closure -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" - -execute_flow -compile diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_qsys.tcl b/projects/ad_fmclidar1_ebz/a10soc/system_qsys.tcl deleted file mode 100644 index e0e89a310ec..00000000000 --- a/projects/ad_fmclidar1_ebz/a10soc/system_qsys.tcl +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Configurable parameters -set SAMPLE_RATE_MHZ 1000.0 -set NUM_OF_CHANNELS 4 ; # M -set SAMPLES_PER_FRAME 1 ; # S -set NUM_OF_LANES 4 ; # L -set ADC_RESOLUTION 8 ; # N & NP - -set LANE_RATE [expr {($ADC_RESOLUTION * $NUM_OF_CHANNELS *$SAMPLE_RATE_MHZ * 1.25) / $NUM_OF_LANES}] - -source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl - -if [info exists ad_project_dir] { - source ../../common/ad_fmclidar1_ebz_qsys.tcl -} else { - source ../common/ad_fmclidar1_ebz_qsys.tcl -} - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -#system ID -set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} -set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "$mem_init_sys_file_path/mem_init_sys.txt" -set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} - -set sys_cstring "SAMPLE_RATE_MHZ=$SAMPLE_RATE_MHZ\ -M=$NUM_OF_CHANNELS\ -S=$SAMPLES_PER_FRAME\ -L=$NUM_OF_LANES\ -NP=$ADC_RESOLUTION\ -LR=$LANE_RATE" - -sysid_gen_sys_init_file $sys_cstring - -#spi -set_instance_parameter_value sys_spi {clockPhase} {1} -set_instance_parameter_value sys_spi {clockPolarity} {1} diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_top.v b/projects/ad_fmclidar1_ebz/a10soc/system_top.v deleted file mode 100644 index 3a6eeb21e86..00000000000 --- a/projects/ad_fmclidar1_ebz/a10soc/system_top.v +++ /dev/null @@ -1,374 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - input sys_resetn, - - // hps-ddr4 (32) - - input hps_ddr_ref_clk, - output [ 0:0] hps_ddr_clk_p, - output [ 0:0] hps_ddr_clk_n, - output [ 16:0] hps_ddr_a, - output [ 1:0] hps_ddr_ba, - output [ 0:0] hps_ddr_bg, - output [ 0:0] hps_ddr_cke, - output [ 0:0] hps_ddr_cs_n, - output [ 0:0] hps_ddr_odt, - output [ 0:0] hps_ddr_reset_n, - output [ 0:0] hps_ddr_act_n, - output [ 0:0] hps_ddr_par, - input [ 0:0] hps_ddr_alert_n, - inout [ 3:0] hps_ddr_dqs_p, - inout [ 3:0] hps_ddr_dqs_n, - inout [ 31:0] hps_ddr_dq, - inout [ 3:0] hps_ddr_dbi_n, - input hps_ddr_rzq, - - // hps-ethernet - - input [ 0:0] hps_eth_rxclk, - input [ 0:0] hps_eth_rxctl, - input [ 3:0] hps_eth_rxd, - output [ 0:0] hps_eth_txclk, - output [ 0:0] hps_eth_txctl, - output [ 3:0] hps_eth_txd, - output [ 0:0] hps_eth_mdc, - inout [ 0:0] hps_eth_mdio, - - // hps-sdio - - output [ 0:0] hps_sdio_clk, - inout [ 0:0] hps_sdio_cmd, - inout [ 7:0] hps_sdio_d, - - // hps-usb - - input [ 0:0] hps_usb_clk, - input [ 0:0] hps_usb_dir, - input [ 0:0] hps_usb_nxt, - output [ 0:0] hps_usb_stp, - inout [ 7:0] hps_usb_d, - - // hps-uart - - input [ 0:0] hps_uart_rx, - output [ 0:0] hps_uart_tx, - - // hps-i2c (shared w fmc-a, fmc-b) - - inout [ 0:0] hps_i2c_sda, - inout [ 0:0] hps_i2c_scl, - - // hps-gpio (max-v-u16) - - inout [ 3:0] hps_gpio, - - // gpio (max-v-u21) - - input [ 7:0] gpio_bd_i, - output [ 3:0] gpio_bd_o, - - // lane interface - - input rx_ref_clk, - input rx_device_clk, - input rx_sysref, - output rx_sync_0, - output rx_sync_1, - input [ 3:0] rx_data, - - input adc_fdb, - input adc_fda, - output adc_pdwn, - - // DAQ board's ADC SPI - - output spi_adc_csn, - output spi_adc_clk, - output spi_adc_mosi, - input spi_adc_miso, - - // DAQ board's clock chip - - output spi_clkgen_csn, - output spi_clkgen_clk, - output spi_clkgen_mosi, - input spi_clkgen_miso, - - // DAQ board's vco chip - - output spi_vco_csn, - output spi_vco_clk, - output spi_vco_mosi, - - // AFE board's DAC - - inout afe_dac_sda, - inout afe_dac_scl, - output afe_dac_clr_n, - output afe_dac_load, - - // AFE board's ADC - - output afe_adc_sclk, - output afe_adc_scn, - input afe_adc_sdi, - output afe_adc_convst, - - // Laser driver differential line - - output laser_driver, - - output laser_driver_en_n, - input laser_driver_otw_n, - - // GPIO's for the laser board - - inout [13:0] laser_gpio, - - // Vref selects for AFE board - - output [ 7:0] tia_chsel -); - - // internal signals - - wire [63:0] gpio_o; - wire [63:0] gpio_i; - wire sys_resetn_s; - wire rx_sync_s; - - // assignments - - // gpio in & out are separate cores - - assign gpio_i[51:38] = gpio_o[51:38]; - - assign afe_adc_convst = gpio_o[37]; - assign afe_dac_load = gpio_o[36]; - assign afe_dac_clr_n = gpio_o[35]; - assign adc_pdwn = gpio_o[34]; - - assign gpio_i[33] = adc_fda; - assign gpio_i[32] = adc_fdb; - - // board stuff (max-v-u21) - - assign gpio_i[31:12] = gpio_o[31:12]; - assign gpio_i[11: 4] = gpio_bd_i; - assign gpio_i[ 3: 0] = gpio_o[ 3: 0]; - assign gpio_bd_o = gpio_o[3:0]; - - assign rx_sync_0 = rx_sync_s; - assign rx_sync_1 = rx_sync_s; - - // peripheral reset - - assign sys_resetn_s = sys_resetn & sys_hps_resetn; - - // instantiations - - wire adc_tia_chsel_en_s; - wire [31:0] adc_data_tia_chsel_s; - - util_tia_chsel #( - .DATA_WIDTH (32) - ) i_util_tia_chsel ( - .clk (rx_device_clk), - .adc_tia_chsel_en (laser_driver), - .adc_data_tia_chsel (adc_data_tia_chsel_s), - .tia_chsel (tia_chsel)); - - wire dma_sync_s; - wire fifo_wr_en_s; - - util_axis_syncgen #( - .ASYNC_SYNC (1) - ) i_util_axis_syncgen ( - .s_axis_aclk (rx_device_clk), - .s_axis_aresetn (1'b1), - .s_axis_ready (1'b1), - .s_axis_valid (fifo_wr_en_s), - .ext_sync (laser_driver), - .s_axis_sync (dma_sync_s)); - - // IO Buffers for I2C - - wire i2c_0_scl_out; - wire i2c_0_scl_in; - wire i2c_0_sda_in; - wire i2c_0_sda_oe; - - ALT_IOBUF scl_iobuf ( - .i(1'b0), - .oe(i2c_0_scl_out), - .o(i2c_0_scl_in), - .io(afe_dac_scl)); - - ALT_IOBUF sda_iobuf ( - .i(1'b0), - .oe(i2c_0_sda_oe), - .o(i2c_0_sda_in), - .io(afe_dac_sda)); - - // Block design instance - - system_bd i_system_bd ( - .sys_clk_clk (sys_clk), - .sys_gpio_bd_in_port (gpio_i[31:0]), - .sys_gpio_bd_out_port (gpio_o[31:0]), - .sys_gpio_in_export (gpio_i[63:32]), - .sys_gpio_out_export (gpio_o[63:32]), - .pr_rom_data_nc_rom_data('h0), - .sys_hps_ddr_mem_ck (hps_ddr_clk_p), - .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), - .sys_hps_ddr_mem_a (hps_ddr_a), - .sys_hps_ddr_mem_act_n (hps_ddr_act_n), - .sys_hps_ddr_mem_ba (hps_ddr_ba), - .sys_hps_ddr_mem_bg (hps_ddr_bg), - .sys_hps_ddr_mem_cke (hps_ddr_cke), - .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), - .sys_hps_ddr_mem_odt (hps_ddr_odt), - .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), - .sys_hps_ddr_mem_par (hps_ddr_par), - .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), - .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), - .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), - .sys_hps_ddr_mem_dq (hps_ddr_dq), - .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), - .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), - .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), - .sys_hps_ddr_rstn_reset_n (sys_resetn), - .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), - .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), - .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), - .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), - .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), - .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), - .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), - .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), - .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), - .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), - .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), - .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), - .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), - .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), - .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), - .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), - .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), - .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), - .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), - .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), - .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), - .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), - .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), - .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), - .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), - .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), - .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), - .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), - .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), - .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), - .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), - .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), - .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), - .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), - .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), - .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), - .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), - .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), - .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), - .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), - .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), - .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), - .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), - .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), - .sys_hps_out_rstn_reset_n (sys_hps_resetn), - .sys_hps_rstn_reset_n (sys_resetn), - .sys_rstn_reset_n (sys_resetn_s), - // AFE's DAC I2C interface - .sys_hps_i2c_0_sda_i (i2c_0_sda_in), - .sys_hps_i2c_0_sda_oe (i2c_0_sda_oe), - .sys_hps_i2c_0_scl_out_clk (i2c_0_scl_out), - .sys_hps_i2c_0_scl_in_clk (i2c_0_scl_in), - // SPI interface for ADC (AD9694) - .sys_spi_MISO (spi_adc_miso), - .sys_spi_MOSI (spi_adc_mosi), - .sys_spi_SCLK (spi_adc_clk), - .sys_spi_SS_n (spi_adc_csn), - // SPI interface for DAQ's clock chip - .sys_spi_clockgen_MISO (spi_clkgen_miso), - .sys_spi_clockgen_MOSI (spi_clkgen_mosi), - .sys_spi_clockgen_SCLK (spi_clkgen_clk), - .sys_spi_clockgen_SS_n (spi_clkgen_csn), - // SPI interface for DAQ's VCO - .sys_spi_vco_MISO (spi_vco_mosi), - .sys_spi_vco_MOSI (spi_vco_mosi), - .sys_spi_vco_SCLK (spi_vco_clk), - .sys_spi_vco_SS_n (spi_vco_csn), - // SPI interface for AFE's ADC chip - .sys_spi_afe_adc_MISO (afe_adc_sdi), - .sys_spi_afe_adc_MOSI (), - .sys_spi_afe_adc_SCLK (afe_adc_sclk), - .sys_spi_afe_adc_SS_n (afe_adc_scn), - // JESD204B for AD9694 - .rx_data_rx_serial_data (rx_data), - .rx_ref_clk_clk (rx_ref_clk), - .rx_sync_export (rx_sync_s), - .rx_sysref_export (rx_sysref), - .rx_device_clk_clk(rx_device_clk), - // laser driver related ports - .laser_driver_driver_pulse (laser_driver), - .laser_driver_en_n_driver_en_n (laser_driver_en_n), - .laser_driver_otw_n_driver_otw_n (laser_driver_otw_n), - .tia_chsel_tia_chsel (tia_chsel), - .laser_gpio_export (laser_gpio), - // Dummy ADC channel for TIA - .adc_data_tia_chsel_data (adc_data_tia_chsel_s), - .adc_data_tia_chsel_valid (1'b1), - .adc_data_tia_chsel_enable (1'b1), - // DMA synchronization - .fifo_wr_en_out_valid (fifo_wr_en_s), - .fifo_wr_en_in_valid (fifo_wr_en_s), - .fifo_wr_sync_sync (dma_sync_s)); - -endmodule diff --git a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl b/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl deleted file mode 100644 index ab4db3551b3..00000000000 --- a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl +++ /dev/null @@ -1,211 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl - -# interfaces and IO ports - -create_bd_port -dir I spi_vco_csn_i -create_bd_port -dir O spi_vco_csn_o -create_bd_port -dir I spi_vco_clk_i -create_bd_port -dir O spi_vco_clk_o -create_bd_port -dir I spi_vco_sdo_i -create_bd_port -dir O spi_vco_sdo_o -create_bd_port -dir I spi_vco_sdi_i -create_bd_port -dir I spi_afe_adc_csn_i -create_bd_port -dir O spi_afe_adc_csn_o -create_bd_port -dir I spi_afe_adc_clk_i -create_bd_port -dir O spi_afe_adc_clk_o -create_bd_port -dir I spi_afe_adc_sdo_i -create_bd_port -dir O spi_afe_adc_sdo_o -create_bd_port -dir I spi_afe_adc_sdi_i -create_bd_port -dir O laser_driver -create_bd_port -dir O laser_driver_en_n -create_bd_port -dir I laser_driver_otw_n -create_bd_port -dir O -from 7 -to 0 tia_chsel - -# NOTE: adc peripherals - controlled by PS7/SPI0 - -# AD9694 data interface - JESD204B framework - -ad_ip_instance axi_adxcvr axi_ad9694_xcvr [list \ - NUM_OF_LANES $NUM_OF_LANES \ - QPLL_ENABLE 1 \ - TX_OR_RX_N 0 \ -] - -adi_axi_jesd204_rx_create ad9694_jesd $NUM_OF_LANES -adi_tpl_jesd204_rx_create ad9694_tpl_core $NUM_OF_LANES \ - $NUM_OF_CHANNELS \ - $SAMPLES_PER_FRAME \ - $SAMPLE_WIDTH \ - 4 \ - $SAMPLE_WIDTH - -ad_ip_instance util_cpack2 util_ad9694_cpack [list \ - NUM_OF_CHANNELS [expr $NUM_OF_CHANNELS + 1] \ - SAMPLES_PER_CHANNEL [expr $CHANNEL_DATA_WIDTH / $SAMPLE_WIDTH] \ - SAMPLE_DATA_WIDTH $SAMPLE_WIDTH \ -] - -ad_ip_instance axi_dmac ad9694_dma [list \ - DMA_TYPE_SRC 1 \ - DMA_TYPE_DEST 0 \ - DMA_DATA_WIDTH_SRC $DMA_DATA_WIDTH \ - DMA_DATA_WIDTH_DEST 64 \ - SYNC_TRANSFER_START 1 \ - FIFO_SIZE 32 \ -] - -# 3-wire SPI for clock synthesizer & VCO - 12.5MHz SCLK rate - -ad_ip_instance axi_quad_spi axi_spi_vco [list \ - C_USE_STARTUP 0 \ - C_NUM_SS_BITS 1 \ - C_SCK_RATIO 8 \ -] - -# 3-wire SPI for AFE board's ADC - 12.5MHz SCLK rate - -ad_ip_instance axi_quad_spi axi_spi_afe_adc [list \ - C_USE_STARTUP 0 \ - C_NUM_SS_BITS 1 \ - C_SCK_RATIO 8 \ -] - -# shared transceiver core - -ad_ip_instance util_adxcvr util_ad9694_xcvr [list \ - RX_NUM_OF_LANES $NUM_OF_LANES \ - TX_NUM_OF_LANES 0 \ -] - -ad_connect $sys_cpu_resetn util_ad9694_xcvr/up_rstn -ad_connect $sys_cpu_clk util_ad9694_xcvr/up_clk - -# laser driver - runs in asynchronous mode, using a 250MHz reference clock -# NOTE: After power up the driver will not generate any pulses, the software -# must configure the AXI Memory Mapped registers and load the configuration. -# This is why the parameter PULSE_PERIOD is 0. - -ad_ip_instance axi_laser_driver axi_laser_driver_0 [list \ - ASYNC_CLK_EN 1 \ - PULSE_WIDTH 1 \ - PULSE_PERIOD 0 \ -] - -# a synchronization module, which make sure that the DMA will catch the pulse as -# its sync signal -create_bd_cell -type module -reference util_axis_syncgen util_axis_syncgen_0 -set_property -dict [list CONFIG.ASYNC_SYNC {0}] [get_bd_cells util_axis_syncgen_0] - -# software needs to know the used TIA channel selection for each transfer, so -# we create an addition dummy ADC channel whit this information -create_bd_cell -type module -reference util_tia_chsel util_tia_chsel_0 -set_property -dict [list CONFIG.DATA_WIDTH {32}] [get_bd_cells util_tia_chsel_0] - -# reference clocks & resets - -create_bd_port -dir I -type clk rx_ref_clk -create_bd_port -dir I -type clk rx_device_clk - -ad_xcvrpll rx_ref_clk util_ad9694_xcvr/qpll_ref_clk_* -ad_xcvrpll rx_ref_clk util_ad9694_xcvr/cpll_ref_clk_* -ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_ad9694_xcvr/up_qpll_rst_* -ad_xcvrpll axi_ad9694_xcvr/up_pll_rst util_ad9694_xcvr/up_cpll_rst_* - -# connections (adc) - -ad_xcvrcon util_ad9694_xcvr axi_ad9694_xcvr ad9694_jesd {3 2 0 1} rx_device_clk -ad_connect rx_device_clk ad9694_tpl_core/link_clk -ad_connect ad9694_jesd/rx_sof ad9694_tpl_core/link_sof -ad_connect ad9694_jesd/rx_data_tvalid ad9694_tpl_core/link_valid -ad_connect ad9694_jesd/rx_data_tdata ad9694_tpl_core/link_data - -ad_connect rx_device_clk util_ad9694_cpack/clk - -for {set i 0} {$i < $NUM_OF_CHANNELS} {incr i} { - ad_connect ad9694_tpl_core/adc_enable_$i util_ad9694_cpack/enable_$i - ad_connect ad9694_tpl_core/adc_data_$i util_ad9694_cpack/fifo_wr_data_$i -} -ad_connect ad9694_tpl_core/adc_valid_0 util_ad9694_cpack/fifo_wr_en -ad_connect ad9694_tpl_core/adc_dovf GND - -ad_connect rx_device_clk ad9694_dma/s_axis_aclk -ad_connect util_ad9694_cpack/packed_fifo_wr_en ad9694_dma/s_axis_valid -ad_connect util_ad9694_cpack/packed_fifo_wr_data ad9694_dma/s_axis_data -ad_connect $sys_dma_resetn ad9694_dma/m_dest_axi_aresetn - -#ad_connect ad9694_tpl_core/adc_dovf axi_ad9694_fifo/adc_wovf - -ad_connect $sys_cpu_clk axi_spi_vco/ext_spi_clk -ad_connect spi_vco_csn_i axi_spi_vco/ss_i -ad_connect spi_vco_csn_o axi_spi_vco/ss_o -ad_connect spi_vco_clk_i axi_spi_vco/sck_i -ad_connect spi_vco_clk_o axi_spi_vco/sck_o -ad_connect spi_vco_sdo_i axi_spi_vco/io0_i -ad_connect spi_vco_sdo_o axi_spi_vco/io0_o -ad_connect spi_vco_sdi_i axi_spi_vco/io1_i - -ad_connect $sys_cpu_clk axi_spi_afe_adc/ext_spi_clk -ad_connect spi_afe_adc_csn_i axi_spi_afe_adc/ss_i -ad_connect spi_afe_adc_csn_o axi_spi_afe_adc/ss_o -ad_connect spi_afe_adc_clk_i axi_spi_afe_adc/sck_i -ad_connect spi_afe_adc_clk_o axi_spi_afe_adc/sck_o -ad_connect spi_afe_adc_sdo_i axi_spi_afe_adc/io0_i -ad_connect spi_afe_adc_sdo_o axi_spi_afe_adc/io0_o -ad_connect spi_afe_adc_sdi_i axi_spi_afe_adc/io1_i - -# laser driver and sync synchronizer - -ad_connect rx_device_clk axi_laser_driver_0/ext_clk -ad_connect laser_driver axi_laser_driver_0/driver_pulse -ad_connect laser_driver_en_n axi_laser_driver_0/driver_en_n -ad_connect laser_driver_otw_n axi_laser_driver_0/driver_otw_n -ad_connect axi_laser_driver_0/driver_dp_reset util_ad9694_cpack/reset -ad_connect tia_chsel axi_laser_driver_0/tia_chsel - -ad_connect rx_device_clk util_axis_syncgen_0/s_axis_aclk -ad_connect util_axis_syncgen_0/s_axis_aresetn VCC -ad_connect util_axis_syncgen_0/s_axis_valid util_ad9694_cpack/packed_fifo_wr_en -ad_connect util_axis_syncgen_0/s_axis_ready VCC -ad_connect util_axis_syncgen_0/ext_sync axi_laser_driver_0/driver_pulse -ad_connect util_axis_syncgen_0/s_axis_sync ad9694_dma/s_axis_user - -# connect the dummy ADC channel to cpack -- channel is always active - -ad_connect rx_device_clk util_tia_chsel_0/clk -ad_connect util_ad9694_cpack/fifo_wr_data_$NUM_OF_CHANNELS util_tia_chsel_0/adc_data_tia_chsel -ad_connect axi_laser_driver_0/driver_pulse util_tia_chsel_0/adc_tia_chsel_en -ad_connect util_ad9694_cpack/enable_$NUM_OF_CHANNELS VCC -ad_connect axi_laser_driver_0/tia_chsel util_tia_chsel_0/tia_chsel - -# interconnect (cpu) - -ad_cpu_interconnect 0x44A50000 axi_ad9694_xcvr -ad_cpu_interconnect 0x44A10000 ad9694_tpl_core -ad_cpu_interconnect 0x44AA0000 ad9694_jesd -ad_cpu_interconnect 0x7c400000 ad9694_dma -ad_cpu_interconnect 0x7c500000 axi_spi_vco -ad_cpu_interconnect 0x7c600000 axi_spi_afe_adc -ad_cpu_interconnect 0x7c700000 axi_laser_driver_0 - -# gt uses hp3, and 100MHz clock for both DRP and AXI4 - -ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9694_xcvr/m_axi - -# interconnect (mem/dac) - -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi - -# interrupts - -ad_cpu_interrupt ps-11 mb-14 ad9694_jesd/irq -ad_cpu_interrupt ps-13 mb-12 ad9694_dma/irq -ad_cpu_interrupt ps-10 mb-15 axi_spi_vco/ip2intc_irpt -ad_cpu_interrupt ps-9 mb-8 axi_spi_afe_adc/ip2intc_irpt -ad_cpu_interrupt ps-8 mb-7 axi_laser_driver_0/irq diff --git a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_qsys.tcl b/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_qsys.tcl deleted file mode 100644 index 908c1caad4c..00000000000 --- a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_qsys.tcl +++ /dev/null @@ -1,236 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# interfaces and IO ports - -# NOTE: For the ADC SPI we are using the sys_spi instance of the base design - -# SPI interface for DAQ's clock chip - fSCLK = 10 MHz - -add_instance sys_spi_clockgen altera_avalon_spi -set_instance_parameter_value sys_spi_clockgen {clockPhase} {0} -set_instance_parameter_value sys_spi_clockgen {clockPolarity} {0} -set_instance_parameter_value sys_spi_clockgen {dataWidth} {8} -set_instance_parameter_value sys_spi_clockgen {masterSPI} {1} -set_instance_parameter_value sys_spi_clockgen {numberOfSlaves} {8} -set_instance_parameter_value sys_spi_clockgen {targetClockRate} {10000000.0} - -add_connection sys_clk.clk_reset sys_spi_clockgen.reset -add_connection sys_clk.clk sys_spi_clockgen.clk -add_interface sys_spi_clockgen conduit end -set_interface_property sys_spi_clockgen EXPORT_OF sys_spi_clockgen.external - -# SPI interface for DAQ's VCO chip - fSCLK = 10 MHz - -add_instance sys_spi_vco altera_avalon_spi -set_instance_parameter_value sys_spi_vco {clockPhase} {0} -set_instance_parameter_value sys_spi_vco {clockPolarity} {0} -set_instance_parameter_value sys_spi_vco {dataWidth} {8} -set_instance_parameter_value sys_spi_vco {masterSPI} {1} -set_instance_parameter_value sys_spi_vco {numberOfSlaves} {8} -set_instance_parameter_value sys_spi_vco {targetClockRate} {10000000.0} - -add_connection sys_clk.clk_reset sys_spi_vco.reset -add_connection sys_clk.clk sys_spi_vco.clk -add_interface sys_spi_vco conduit end -set_interface_property sys_spi_vco EXPORT_OF sys_spi_vco.external - -# I2C interface for AFE's DAC chip - activate the second I2C HPS interface - -set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA} -set_instance_parameter_value sys_hps {I2C0_Mode} {default} - -add_interface sys_hps_i2c_0 conduit end -set_interface_property sys_hps_i2c_0 EXPORT_OF sys_hps.i2c0 -add_interface sys_hps_i2c_0_scl_out clock source -set_interface_property sys_hps_i2c_0_scl_out EXPORT_OF sys_hps.i2c0_clk -add_interface sys_hps_i2c_0_scl_in clock sink -set_interface_property sys_hps_i2c_0_scl_in EXPORT_OF sys_hps.i2c0_scl_in - -# SPI interface for AFE's ADC chip - fSCLK = 10 MHz - -add_instance sys_spi_afe_adc altera_avalon_spi -set_instance_parameter_value sys_spi_afe_adc {clockPhase} {0} -set_instance_parameter_value sys_spi_afe_adc {clockPolarity} {1} -set_instance_parameter_value sys_spi_afe_adc {dataWidth} {8} -set_instance_parameter_value sys_spi_afe_adc {masterSPI} {1} -set_instance_parameter_value sys_spi_afe_adc {numberOfSlaves} {8} -set_instance_parameter_value sys_spi_afe_adc {targetClockRate} {10000000.0} - -add_connection sys_clk.clk_reset sys_spi_afe_adc.reset -add_connection sys_clk.clk sys_spi_afe_adc.clk -add_interface sys_spi_afe_adc conduit end -set_interface_property sys_spi_afe_adc EXPORT_OF sys_spi_afe_adc.external - -# AD9694 data interface - JESD204B interface framework - -add_instance ad9694_jesd204 adi_jesd204 -set_instance_parameter_value ad9694_jesd204 {ID} {0} -set_instance_parameter_value ad9694_jesd204 {TX_OR_RX_N} {0} -set_instance_parameter_value ad9694_jesd204 {LANE_RATE} $LANE_RATE -set_instance_parameter_value ad9694_jesd204 {NUM_OF_LANES} $NUM_OF_LANES -set_instance_parameter_value ad9694_jesd204 {REFCLK_FREQUENCY} {250} -set_instance_parameter_value ad9694_jesd204 {SOFT_PCS} {true} -set_instance_parameter_value ad9694_jesd204 {EXT_DEVICE_CLK_EN} {true} -set_instance_parameter_value ad9694_jesd204 {LANE_MAP} "3 2 0 1" - -add_connection sys_clk.clk ad9694_jesd204.sys_clk -add_connection sys_clk.clk_reset ad9694_jesd204.sys_resetn -add_interface rx_ref_clk clock sink -set_interface_property rx_ref_clk EXPORT_OF ad9694_jesd204.ref_clk -add_interface rx_data conduit end -set_interface_property rx_data EXPORT_OF ad9694_jesd204.serial_data -add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF ad9694_jesd204.sysref -add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF ad9694_jesd204.sync - -add_instance rx_device_clock altera_clock_bridge -add_interface rx_device_clk clock sink -set_interface_property rx_device_clk EXPORT_OF rx_device_clock.in_clk - -add_connection rx_device_clock.out_clk ad9694_jesd204.device_clk - -# JESD204B - Transport Layer - -add_instance axi_ad9694 ad_ip_jesd204_tpl_adc -set_instance_parameter_value axi_ad9694 {NUM_LANES} $NUM_OF_LANES -set_instance_parameter_value axi_ad9694 {NUM_CHANNELS} $NUM_OF_CHANNELS -set_instance_parameter_value axi_ad9694 {BITS_PER_SAMPLE} $ADC_RESOLUTION -set_instance_parameter_value axi_ad9694 {DMA_BITS_PER_SAMPLE} $ADC_RESOLUTION -set_instance_parameter_value axi_ad9694 {CONVERTER_RESOLUTION} $ADC_RESOLUTION -set_instance_parameter_value axi_ad9694 {SAMPLES_PER_FRAME} {1} -set_instance_parameter_value axi_ad9694 {OCTETS_PER_FRAME} {1} - -add_connection rx_device_clock.out_clk axi_ad9694.link_clk -add_connection axi_ad9694.if_link_sof ad9694_jesd204.link_sof -add_connection ad9694_jesd204.link_data axi_ad9694.link_data -add_connection sys_clk.clk_reset axi_ad9694.s_axi_reset -add_connection sys_clk.clk axi_ad9694.s_axi_clock - -# channel packing and DMA instance (plus one dummy channel for TIA_CHSEL) - -## NOTE: we round up the NUM_OF_CHANNELS to the next power of two -add_instance util_ad9694_cpack util_cpack2 -set_instance_parameter_value util_ad9694_cpack {NUM_OF_CHANNELS} {8} -set_instance_parameter_value util_ad9694_cpack {SAMPLES_PER_CHANNEL} {4} -set_instance_parameter_value util_ad9694_cpack {SAMPLE_DATA_WIDTH} {8} - -add_connection rx_device_clock.out_clk util_ad9694_cpack.clk - -for {set i 0} {$i < $NUM_OF_CHANNELS} {incr i} { - add_connection axi_ad9694.adc_ch_$i util_ad9694_cpack.adc_ch_$i -} - -# Increase the dma_clk frequency and the data width of the F2SDRAM interface, -# so we can stream 1kSPS@50kHz -set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {250} -set_instance_parameter_value sys_hps {F2SDRAM_PORT_CONFIG} {7} - -add_instance axi_ad9694_dma axi_dmac -set_instance_parameter_value axi_ad9694_dma {DMA_DATA_WIDTH_SRC} {256} -set_instance_parameter_value axi_ad9694_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_ad9694_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_ad9694_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9694_dma {SYNC_TRANSFER_START} {1} -set_instance_parameter_value axi_ad9694_dma {CYCLIC} {0} -set_instance_parameter_value axi_ad9694_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_ad9694_dma {DMA_TYPE_SRC} {2} -set_instance_parameter_value axi_ad9694_dma {FIFO_SIZE} {32} - -add_connection rx_device_clock.out_clk axi_ad9694_dma.if_fifo_wr_clk -add_connection sys_clk.clk axi_ad9694_dma.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9694_dma.s_axi_reset -add_connection sys_dma_clk.clk axi_ad9694_dma.m_dest_axi_clock -add_connection sys_dma_clk.clk_reset axi_ad9694_dma.m_dest_axi_reset - -add_connection util_ad9694_cpack.if_packed_fifo_wr_data axi_ad9694_dma.if_fifo_wr_din -add_connection util_ad9694_cpack.if_packed_fifo_wr_overflow axi_ad9694_dma.if_fifo_wr_overflow -add_connection util_ad9694_cpack.if_fifo_wr_overflow axi_ad9694.if_adc_dovf - -ad_dma_interconnect axi_ad9694_dma.m_dest_axi - -# laser driver - runs in asynchronous mode, using a 250MHz reference clock -# NOTE: After power up the driver will not generate any pulses, the software -# must configure the AXI Memory Mapped registers and load the configuration. -# This is why the parameter PULSE_PERIOD is 0. - -add_instance axi_laser_driver_0 axi_laser_driver -set_instance_parameter_value axi_laser_driver_0 {ASYNC_CLK_EN} {1} -set_instance_parameter_value axi_laser_driver_0 {PULSE_WIDTH} {1} -set_instance_parameter_value axi_laser_driver_0 {PULSE_PERIOD} {0} - -add_connection sys_clk.clk axi_laser_driver_0.s_axi_clock -add_connection sys_clk.clk_reset axi_laser_driver_0.s_axi_reset - -# laser driver and sync synchronizer - -add_connection rx_device_clock.out_clk axi_laser_driver_0.if_ext_clk - -add_interface laser_driver conduit end -set_interface_property laser_driver EXPORT_OF axi_laser_driver_0.if_driver_pulse -add_interface laser_driver_en_n conduit end -set_interface_property laser_driver_en_n EXPORT_OF axi_laser_driver_0.if_driver_en_n -add_interface laser_driver_otw_n conduit end -set_interface_property laser_driver_otw_n EXPORT_OF axi_laser_driver_0.if_driver_otw_n -add_interface tia_chsel conduit end -set_interface_property tia_chsel EXPORT_OF axi_laser_driver_0.if_tia_chsel - -add_connection axi_laser_driver_0.if_driver_dp_reset util_ad9694_cpack.reset - -# the synchronization module, which make sure that the DMA will catch the pulse as -# its sync signal, is instantiate in system_top, export all the necessary signals - -add_interface fifo_wr_en_out conduit end -set_interface_property fifo_wr_en_out EXPORT_OF util_ad9694_cpack.if_packed_fifo_wr_en -add_interface fifo_wr_en_in conduit end -set_interface_property fifo_wr_en_in EXPORT_OF axi_ad9694_dma.if_fifo_wr_en -add_interface fifo_wr_sync conduit end -set_interface_property fifo_wr_sync EXPORT_OF axi_ad9694_dma.if_sync - -# software needs to know the used TIA channel selection for each transfer, so -# we create an addition dummy ADC channel whit this information - -add_interface adc_data_tia_chsel conduit end -set_interface_property adc_data_tia_chsel EXPORT_OF util_ad9694_cpack.adc_ch_$NUM_OF_CHANNELS - -# laser GPIOs - -add_instance avl_laser_gpio altera_avalon_pio -set_instance_parameter_value avl_laser_gpio {direction} {Bidir} -set_instance_parameter_value avl_laser_gpio {generateIRQ} {1} -set_instance_parameter_value avl_laser_gpio {width} {14} -add_connection sys_clk.clk avl_laser_gpio.clk -add_connection sys_clk.clk_reset avl_laser_gpio.reset -add_interface laser_gpio conduit end -set_interface_property laser_gpio EXPORT_OF avl_laser_gpio.external_connection - -# base addresses - -ad_cpu_interconnect 0x00000060 sys_spi_clockgen.spi_control_port -ad_cpu_interconnect 0x00000080 sys_spi_vco.spi_control_port -ad_cpu_interconnect 0x000000A0 sys_spi_afe_adc.spi_control_port -ad_cpu_interconnect 0x00040000 ad9694_jesd204.link_reconfig -ad_cpu_interconnect 0x00044000 ad9694_jesd204.link_management -ad_cpu_interconnect 0x00045000 ad9694_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00048000 ad9694_jesd204.phy_reconfig_0 -ad_cpu_interconnect 0x00049000 ad9694_jesd204.phy_reconfig_1 -ad_cpu_interconnect 0x0004a000 ad9694_jesd204.phy_reconfig_2 -ad_cpu_interconnect 0x0004b000 ad9694_jesd204.phy_reconfig_3 -ad_cpu_interconnect 0x0004c000 axi_ad9694_dma.s_axi -ad_cpu_interconnect 0x00050000 axi_ad9694.s_axi -ad_cpu_interconnect 0x00060000 axi_laser_driver_0.s_axi -ad_cpu_interconnect 0x00070000 avl_laser_gpio.s1 - -# interrupts - -ad_cpu_interrupt 8 sys_spi_clockgen.irq -ad_cpu_interrupt 9 sys_spi_vco.irq -ad_cpu_interrupt 10 sys_spi_afe_adc.irq -ad_cpu_interrupt 11 ad9694_jesd204.interrupt -ad_cpu_interrupt 12 axi_ad9694_dma.interrupt_sender -ad_cpu_interrupt 13 axi_laser_driver_0.interrupt_sender -ad_cpu_interrupt 14 avl_laser_gpio.irq - diff --git a/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v b/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v deleted file mode 100644 index 174e609a403..00000000000 --- a/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v +++ /dev/null @@ -1,94 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_axis_syncgen #( - - parameter ASYNC_SYNC = 1 -) ( - input s_axis_aclk, - input s_axis_aresetn, - input s_axis_ready, - input s_axis_valid, - - input ext_sync, - output s_axis_sync -); - - wire sync_int_s; - wire sync_ack_s; - wire sync_ack_int_s; - reg synced = 1'b0; - reg sync_int_d = 1'b0; - reg s_axis_sync_int = 1'b0; - - // generate CDC for external sync - - sync_bits #( - .NUM_OF_BITS (1), - .ASYNC_CLK (ASYNC_SYNC) - ) i_axis_ext_sync ( - .in_bits (ext_sync), - .out_clk (s_axis_aclk), - .out_resetn (s_axis_aresetn), - .out_bits (sync_int_s)); - - // generate the sync signal - - assign sync_ack_s = sync_int_s & s_axis_ready & s_axis_valid; - assign sync_ack_int_s = s_axis_sync_int & s_axis_ready & s_axis_valid; - - always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - sync_int_d <= 1'b0; - s_axis_sync_int <= 1'b0; - synced <= 1'b0; - end else begin - sync_int_d <= sync_int_s; - if (sync_int_s && ~sync_int_d) begin - s_axis_sync_int <= 1'b1; - synced <= 1'b0; - end - if (sync_ack_int_s) begin - synced <= 1'b1; - s_axis_sync_int <= 1'b0; - end - end - end - - assign s_axis_sync = s_axis_sync_int | (sync_ack_s & ~synced); - -endmodule diff --git a/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v b/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v deleted file mode 100644 index a8524c2631b..00000000000 --- a/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v +++ /dev/null @@ -1,63 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_tia_chsel #( - - parameter DATA_WIDTH = 32 -) ( - input clk, - - input adc_tia_chsel_en, - output [DATA_WIDTH-1:0] adc_data_tia_chsel, - - input [ 7:0] tia_chsel -); - - (* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int; - - genvar i; - generate - for (i=0; iM22KcWhx{jiItF$c`V74kRq9qF+-(< zL@FB0eEaHopMTrF?fw4sJokNLt#z&QI?rR+kNwz>6=|q{h@OsLWc|I%x7;|YSBIIMZV)c@|c_fG02U)~Zw)P6Mm4ZO51?l8kL@&aPq+ipvI=}gNt6qZxH z^n0@FL+z#9oSd^Gb*t@3dkOBuHg|XTST5!Ms*}99tq}5CimR&jsjAk!%-upyFTk{k z7#JA1&awA&Yk~-2c;dwO>FMD-9`cJXGi*(%5;SW%)&&$hOGTB0% zd93oRI9s77?*ZD3i_cA|Gjd#KN1NV0u%!vP!KEz!{Ck+jr}P7%lRi(9lB{An>n{A7 z=r2C@_wU~rMr>OjvwmEJVb7m0X~BX*Ld}hh1A~Kd&%a9^f8yZb5&Y$K>PPa!ZtK=q zr_Ot&mPOuQUT>tKv90!UY>Hx~prD9h+=PqlChy$Wq59xpOUpZ&ydrz{2(&02CZE-WwC2d!Rw9=2)Qwr!!*^pwPeY(Fm@>W~oo{=ZMuCH$LOhs&C zX7*lR3miAq<_K+&l9hc|?rLFdY&=}y-Z#RfK`Y0o=g8>dR%r3yMD0c2Ko>!Ne)aNg zdheh3DhDh`5wzjYa}Cla#>RSs-@3^Uzki=P`J^UzeQkAl{;j11AK$6vzcZhkW1VD@ z5+#pggL!%rPKt&ao{HDa*2s8R;Y5m{-PR_*DO|%otm08`Z*M~=&5`VGqfG7hHRm53 zukjNQ5FqTFo$uVdDP{L8^jp@oB%e->s%H6wn1&-V%LekPkb_cIWyY%Mu6Jre3$Hd||S|Ym0}t8BH(f^2QnF7p$;k80YtSSeRKD z8cKOjv^O?t5)U6f{Q3KLz|!x0x|)Nu8CS1b;9Q?Da4Grx{bnVT^e*2dSNntS*|Xov zUEkI%f3KOGbQTj6Q%aR&isV$J4r46X`V~8Iw~Rg@ke!7W`>w zXawU2bB^vfcI=o^>W7@8DPdt@uTzz$r>F6k;o)HuVHR)iUpQa*Mz8l<1_p*){nV-9 z${$OArai4y!VFFRvm6;2nGbb=$E>VGNV={?cBfBkw@dFm_fh?R*d(_ei?yXCWBAN) zB~8eK`ZZ2MHE6{$?RdTato^{llVmHL_1D(c7PBZZoo_;9dGQSX{PMJ&-N$d=Y(BGG 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-#################################################################################### - -PROJECT_NAME := ad_fmclidar1_ebz_zc706 - -M_DEPS += ../common/util_tia_chsel.v -M_DEPS += ../common/util_axis_syncgen.v -M_DEPS += ../common/ad_fmclidar1_ebz_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/zc706/zc706_system_constr.xdc -M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_laser_driver -LIB_DEPS += axi_spdif_tx -LIB_DEPS += axi_sysid -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/axi_jesd204_rx -LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += xilinx/axi_adxcvr -LIB_DEPS += xilinx/util_adxcvr - -include ../../scripts/project-xilinx.mk diff --git a/projects/ad_fmclidar1_ebz/zc706/system_bd.tcl b/projects/ad_fmclidar1_ebz/zc706/system_bd.tcl deleted file mode 100644 index 10d2587c7ac..00000000000 --- a/projects/ad_fmclidar1_ebz/zc706/system_bd.tcl +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Configurable parameters -set SAMPLE_RATE_MHZ 1000.0 -set NUM_OF_CHANNELS 4 ; # M -set SAMPLES_PER_FRAME 1 ; # S -set NUM_OF_LANES 4 ; # L -set ADC_RESOLUTION 8 ; # N & NP - -# Auto-computed parameters - -set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS] -set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS] -# we have to calculate with an additional dummy channel for TIA -set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH > 127 ? 256 : \ - $ADC_DATA_WIDTH > 63 ? 128 : 64] -set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8] - -# add RTL sources which will be instantiated in system_bd directly -adi_project_files ad_fmclidar1_ebz_zc706 [list \ - "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ - "../common/util_tia_chsel.v" \ - "../common/util_axis_syncgen.v" ] - -# source all the block designs -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source ../common/ad_fmclidar1_ebz_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -# I2C for AFE board's DAC - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac - -ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_IO1_ENABLE 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 1 - -ad_connect iic_dac sys_ps7/IIC_1 - -# System ID instance and configuration -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -set sys_cstring "SAMPLE_RATE_MHZ=$SAMPLE_RATE_MHZ\ -M=$NUM_OF_CHANNELS\ -S=$SAMPLES_PER_FRAME\ -L=$NUM_OF_LANES\ -NP=$ADC_RESOLUTION\ -CHANNEL_DATA_WIDTH=$CHANNEL_DATA_WIDTH\ -ADC_DATA_WIDTH=$ADC_DATA_WIDTH\ -DMA_DATA_WIDTH=$DMA_DATA_WIDTH\ -SAMPLE_WIDTH=$SAMPLE_WIDTH" - -sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad_fmclidar1_ebz/zc706/system_constr.xdc b/projects/ad_fmclidar1_ebz/zc706/system_constr.xdc deleted file mode 100644 index 5ecfb44a658..00000000000 --- a/projects/ad_fmclidar1_ebz/zc706/system_constr.xdc +++ /dev/null @@ -1,110 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ADC digital interface (JESD204B) - -set_property -dict {PACKAGE_PIN AD10 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N - -set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVDS_25} [get_ports rx_device_clk_p] ; ## G02 FMC_HPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS_25} [get_ports rx_device_clk_n] ; ## G03 FMC_HPC_CLK1_M2C_N - -set_property -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N - -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports rx_sync0_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports rx_sync0_n] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync1_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync1_n] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N - -# ADC control lines - -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_pdwn] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## G10 FMC_HPC_LA03_N - -# SPI interfaces - -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_adc_csn] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports spi_adc_clk] ; ## G36 FMC_HPC_LA33_P -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_adc_miso] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports spi_adc_mosi] ; ## G37 FMC_HPC_LA33_N - -set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports spi_vco_csn] ; ## H19 FMC_HPC_LA15_P -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports spi_vco_clk] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports spi_vco_mosi] ; ## H17 FMC_HPC_LA11_N - -set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_csn] ; ## H25 FMC_HPC_LA21_P -set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_clk] ; ## H22 FMC_HPC_LA19_P -set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_miso] ; ## H26 FMC_HPC_LA21_N -set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi_clkgen_mosi] ; ## H23 FMC_HPC_LA19_N - -# Laser driver and GPIOs - -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports laser_driver_p] ; ## C22 FMC_HPC_LA18_CC_P -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports laser_driver_n] ; ## C23 FMC_HPC_LA18_CC_N - -set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports laser_driver_en_n] ; ## C26 FMC_HPC_LA27_P -set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports laser_driver_otw_n] ; ## G33 FMC_HPC_LA31_P - -set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[0]] ; ## C27 FMC_HPC_LA27_N -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports laser_gpio[1]] ; ## D20 FMC_HPC_LA17_CC_P -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports laser_gpio[2]] ; ## D21 FMC_HPC_LA17_CC_N -set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports laser_gpio[3]] ; ## D23 FMC_HPC_LA23_P -set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports laser_gpio[4]] ; ## D24 FMC_HPC_LA23_N -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[5]] ; ## D26 FMC_HPC_LA26_P -set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[6]] ; ## D27 FMC_HPC_LA26_N -set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports laser_gpio[7]] ; ## G24 FMC_HPC_LA22_P -set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports laser_gpio[8]] ; ## G25 FMC_HPC_LA22_N -set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[9]] ; ## G27 FMC_HPC_LA25_P -set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[10]] ; ## G28 FMC_HPC_LA25_N -set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports laser_gpio[11]] ; ## G30 FMC_HPC_LA29_P -set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports laser_gpio[12]] ; ## G31 FMC_HPC_LA29_N -set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N - -# TIA channel selection - -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports tia_chsel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports tia_chsel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports tia_chsel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports tia_chsel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P - -# AFE DAC I2C and control - -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P - -# AFE ADC SPI and control - -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports afe_adc_sclk] ; ## G07 FMC_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports afe_adc_scn] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports afe_adc_convst] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports afe_adc_sdi] ; ## G15 FMC_HPC_LA12_P - -# clocks - -create_clock -period 4.000 -name rx_device_clk [get_ports rx_device_clk_p] -create_clock -period 4.000 -name rx_ref_clk [get_ports rx_ref_clk_p] - -# SYSREF is in phase with the device clock - -set_input_delay -clock [get_clocks rx_device_clk] -rise -max 0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] -set_input_delay -clock [get_clocks rx_device_clk] -rise -min -0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] -set_property IOBDELAY NONE [get_cells -hierarchical -regexp -filter { NAME =~ ".*sysref_r_reg"}] - diff --git a/projects/ad_fmclidar1_ebz/zc706/system_project.tcl b/projects/ad_fmclidar1_ebz/zc706/system_project.tcl deleted file mode 100644 index 07b47d14462..00000000000 --- a/projects/ad_fmclidar1_ebz/zc706/system_project.tcl +++ /dev/null @@ -1,17 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project ad_fmclidar1_ebz_zc706 -adi_project_files ad_fmclidar1_ebz_zc706 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] - -adi_project_run ad_fmclidar1_ebz_zc706 diff --git a/projects/ad_fmclidar1_ebz/zc706/system_top.v b/projects/ad_fmclidar1_ebz/zc706/system_top.v deleted file mode 100644 index b5df15a9a41..00000000000 --- a/projects/ad_fmclidar1_ebz/zc706/system_top.v +++ /dev/null @@ -1,304 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [14:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [23:0] hdmi_data, - - output spdif, - - inout iic_scl, - inout iic_sda, - - input rx_ref_clk_p, - input rx_ref_clk_n, - input rx_device_clk_p, - input rx_device_clk_n, - output rx_sync0_p, - output rx_sync0_n, - output rx_sync1_p, - output rx_sync1_n, - input rx_sysref_p, - input rx_sysref_n, - input [ 3:0] rx_data_p, - input [ 3:0] rx_data_n, - - inout adc_fdb, - inout adc_fda, - inout adc_pdwn, - - // DAQ board's ADC SPI - - output spi_adc_csn, - output spi_adc_clk, - output spi_adc_mosi, - input spi_adc_miso, - - // DAQ board's clock chip - - output spi_clkgen_csn, - output spi_clkgen_clk, - output spi_clkgen_mosi, - input spi_clkgen_miso, - - // DAQ board's vco chip - - output spi_vco_csn, - output spi_vco_clk, - output spi_vco_mosi, - - // AFE board's DAC - - inout afe_dac_sda, - inout afe_dac_scl, - output afe_dac_clr_n, - output afe_dac_load, - - // AFE board's ADC - - output afe_adc_sclk, - output afe_adc_scn, - input afe_adc_sdi, - output afe_adc_convst, - - // Laser driver differential line - - output laser_driver_p, - output laser_driver_n, - - output laser_driver_en_n, - input laser_driver_otw_n, - - // GPIO's for the laser board - - inout [13:0] laser_gpio, - - // Vref selects for AFE board - - output [ 7:0] tia_chsel -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire rx_ref_clk; - wire rx_sync; - wire rx_sysref; - wire rx_device_clk; - wire laser_driver; - - // instantiations - - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - OBUFDS i_obufds_rx_sync0 ( - .I (rx_sync), - .O (rx_sync0_p), - .OB (rx_sync0_n)); - - OBUFDS i_obufds_rx_sync1 ( - .I (rx_sync), - .O (rx_sync1_p), - .OB (rx_sync1_n)); - - IBUFGDS i_rx_device_clk ( - .I (rx_device_clk_p), - .IB (rx_device_clk_n), - .O (rx_device_clk)); - - IBUFDS i_rx_sysref ( - .I (rx_sysref_p), - .IB (rx_sysref_n), - .O (rx_sysref)); - - // laser driver - - OBUFDS i_obufds_laser_driver ( - .I (laser_driver), - .O (laser_driver_p), - .OB (laser_driver_n)); - - // GPIO connections to the FMC connector - - ad_iobuf #( - .DATA_WIDTH(20) - ) i_fmc_iobuf ( - .dio_t ({gpio_t[51:38], 3'b0, gpio_t[34:32]}), - .dio_i ({gpio_o[51:32]}), - .dio_o ({gpio_i[51:32]}), - .dio_p ({ - laser_gpio, // 51:38 - afe_adc_convst, // 37 - output only - afe_dac_load, // 36 - output only - afe_dac_clr_n, // 35 - output only - adc_pdwn, // 34 - adc_fdb, // 33 - adc_fda // 32 - })); - - assign gpio_i[63:52] = 12'b0; - assign gpio_i[31:15] = 17'b0; - - // GPIO connections for the carrier - - ad_iobuf #( - .DATA_WIDTH(15) - ) i_iobuf_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), - .dio_p (gpio_bd)); - - // block design instance - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_data_2_n (rx_data_n[2]), - .rx_data_2_p (rx_data_p[2]), - .rx_data_3_n (rx_data_n[3]), - .rx_data_3_p (rx_data_p[3]), - .rx_ref_clk (rx_ref_clk), - .rx_device_clk (rx_device_clk), - .rx_sync_0 (rx_sync), - .rx_sysref_0 (rx_sysref), - .spdif (spdif), - .laser_driver (laser_driver), - .laser_driver_en_n (laser_driver_en_n), - .laser_driver_otw_n (laser_driver_otw_n), - .tia_chsel (tia_chsel), - .iic_dac_scl_io (afe_dac_scl), - .iic_dac_sda_io (afe_dac_sda), - .spi0_clk_i (spi_adc_clk), - .spi0_clk_o (spi_adc_clk), - .spi0_csn_0_o (spi_adc_csn), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_adc_miso), - .spi0_sdo_i (spi_adc_mosi), - .spi0_sdo_o (spi_adc_mosi), - .spi1_clk_i (spi_clkgen_clk), - .spi1_clk_o (spi_clkgen_clk), - .spi1_csn_0_o (spi_clkgen_csn), - .spi1_csn_i (1'b1), - .spi1_sdi_i (spi_clkgen_miso), - .spi1_sdo_i (spi_clkgen_mosi), - .spi1_sdo_o (spi_clkgen_mosi), - .spi_vco_csn_i (1'b1), - .spi_vco_csn_o (spi_vco_csn), - .spi_vco_clk_i (1'b0), - .spi_vco_clk_o (spi_vco_clk), - .spi_vco_sdo_i (1'b0), - .spi_vco_sdo_o (spi_vco_mosi), - .spi_vco_sdi_i (1'b0), - .spi_afe_adc_csn_i (1'b1), - .spi_afe_adc_csn_o (afe_adc_scn), - .spi_afe_adc_clk_i (1'b0), - .spi_afe_adc_clk_o (afe_adc_sclk), - .spi_afe_adc_sdo_i (1'b0), - .spi_afe_adc_sdo_o (), - .spi_afe_adc_sdi_i (afe_adc_sdi)); - -endmodule diff --git a/projects/ad_fmclidar1_ebz/zcu102/Makefile b/projects/ad_fmclidar1_ebz/zcu102/Makefile deleted file mode 100644 index 06d25a04788..00000000000 --- a/projects/ad_fmclidar1_ebz/zcu102/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := ad_fmclidar1_ebz_zcu102 - -M_DEPS += ../common/util_tia_chsel.v -M_DEPS += ../common/util_axis_syncgen.v -M_DEPS += ../common/ad_fmclidar1_ebz_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc -M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl -M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_laser_driver -LIB_DEPS += axi_sysid -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/axi_jesd204_rx -LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += xilinx/axi_adxcvr -LIB_DEPS += xilinx/util_adxcvr - -include ../../scripts/project-xilinx.mk diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_bd.tcl b/projects/ad_fmclidar1_ebz/zcu102/system_bd.tcl deleted file mode 100644 index deacf5e790a..00000000000 --- a/projects/ad_fmclidar1_ebz/zcu102/system_bd.tcl +++ /dev/null @@ -1,59 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Configurable parameters -set SAMPLE_RATE_MHZ 1000.0 -set NUM_OF_CHANNELS 4 ; # M -set SAMPLES_PER_FRAME 1 ; # S -set NUM_OF_LANES 4 ; # L -set ADC_RESOLUTION 8 ; # N & NP - -# Auto-computed parameters - -set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS] -set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS] -# we have to calculate with an additional dummy channel for TIA -set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH > 127 ? 256 : \ - $ADC_DATA_WIDTH > 63 ? 128 : 64] -set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8] - -# add RTL sources which will be instantiated in system_bd directly -adi_project_files ad_fmclidar1_ebz_zcu102 [list \ - "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ - "../common/util_tia_chsel.v" \ - "../common/util_axis_syncgen.v" ] - -# source all the block designs -source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl -source ../common/ad_fmclidar1_ebz_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -# I2C for AFE board's DAC - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac - -ad_ip_instance axi_iic afe_dac_iic -ad_connect iic_dac afe_dac_iic/iic - -ad_cpu_interconnect 0x7c800000 afe_dac_iic - -ad_cpu_interrupt ps-12 mb-14 afe_dac_iic/iic2intc_irpt - -# System ID instance and configuration -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -set sys_cstring "SAMPLE_RATE_MHZ=$SAMPLE_RATE_MHZ\ -M=$NUM_OF_CHANNELS\ -S=$SAMPLES_PER_FRAME\ -L=$NUM_OF_LANES\ -NP=$ADC_RESOLUTION\ -CHANNEL_DATA_WIDTH=$CHANNEL_DATA_WIDTH\ -ADC_DATA_WIDTH=$ADC_DATA_WIDTH\ -DMA_DATA_WIDTH=$DMA_DATA_WIDTH\ -SAMPLE_WIDTH=$SAMPLE_WIDTH" - -sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc b/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc deleted file mode 100644 index a37c03304df..00000000000 --- a/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc +++ /dev/null @@ -1,109 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ADC digital interface (JESD204B) - -set_property -dict {PACKAGE_PIN G8 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN G7 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N - -set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS} [get_ports rx_device_clk_p] ; ## G02 FMC_HPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS} [get_ports rx_device_clk_n] ; ## G03 FMC_HPC_CLK1_M2C_N - -set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N - -set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS} [get_ports rx_sync0_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS} [get_ports rx_sync0_n] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports rx_sync1_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports rx_sync1_n] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N - -# ADC control lines - -set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports adc_pdwn] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## G10 FMC_HPC_LA03_N - -# SPI interfaces - -set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports spi_adc_csn] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18} [get_ports spi_adc_clk] ; ## G36 FMC_HPC_LA33_P -set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports spi_adc_miso] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS18} [get_ports spi_adc_mosi] ; ## G37 FMC_HPC_LA33_N - -set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports spi_vco_csn] ; ## H19 FMC_HPC_LA15_P -set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports spi_vco_clk] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports spi_vco_mosi] ; ## H17 FMC_HPC_LA11_N - -set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports spi_clkgen_csn] ; ## H25 FMC_HPC_LA21_P -set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports spi_clkgen_clk] ; ## H22 FMC_HPC_LA19_P -set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports spi_clkgen_miso] ; ## H26 FMC_HPC_LA21_N -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports spi_clkgen_mosi] ; ## H23 FMC_HPC_LA19_N - -# Laser driver and GPIOs - -set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVDS} [get_ports laser_driver_p] ; ## C22 FMC_HPC_LA18_CC_P -set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVDS} [get_ports laser_driver_n] ; ## C23 FMC_HPC_LA18_CC_N - -set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports laser_driver_en_n] ; ## C26 FMC_HPC_LA27_P -set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports laser_driver_otw_n] ; ## G33 FMC_HPC_LA31_P - -set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports laser_gpio[0]] ; ## C27 FMC_HPC_LA27_N -set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports laser_gpio[1]] ; ## D20 FMC_HPC_LA17_CC_P -set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports laser_gpio[2]] ; ## D21 FMC_HPC_LA17_CC_N -set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports laser_gpio[3]] ; ## D23 FMC_HPC_LA23_P -set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports laser_gpio[4]] ; ## D24 FMC_HPC_LA23_N -set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports laser_gpio[5]] ; ## D26 FMC_HPC_LA26_P -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports laser_gpio[6]] ; ## D27 FMC_HPC_LA26_N -set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports laser_gpio[7]] ; ## G24 FMC_HPC_LA22_P -set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports laser_gpio[8]] ; ## G25 FMC_HPC_LA22_N -set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports laser_gpio[9]] ; ## G27 FMC_HPC_LA25_P -set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports laser_gpio[10]] ; ## G28 FMC_HPC_LA25_N -set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports laser_gpio[11]] ; ## G30 FMC_HPC_LA29_P -set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports laser_gpio[12]] ; ## G31 FMC_HPC_LA29_N -set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N - -# TIA channel selection - -set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports tia_chsel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports tia_chsel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports tia_chsel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports tia_chsel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P -set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports tia_chsel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N -set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports tia_chsel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports tia_chsel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports tia_chsel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P - -# AFE DAC I2C and control - -set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P - -# AFE ADC SPI and control - -set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18} [get_ports afe_adc_sclk] ; ## G07 FMC_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports afe_adc_scn] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports afe_adc_convst] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports afe_adc_sdi] ; ## G15 FMC_HPC_LA12_P - -# clocks - -create_clock -period 4.000 -name rx_device_clk [get_ports rx_device_clk_p] -create_clock -period 4.000 -name rx_ref_clk [get_ports rx_ref_clk_p] - -# SYSREF is edge-aligned rising edge source synchronous input - -set_input_delay -clock [get_clocks rx_device_clk] [get_property PERIOD [get_clocks rx_device_clk]] \ - [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] - diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_project.tcl b/projects/ad_fmclidar1_ebz/zcu102/system_project.tcl deleted file mode 100644 index ed327a2ff70..00000000000 --- a/projects/ad_fmclidar1_ebz/zcu102/system_project.tcl +++ /dev/null @@ -1,17 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project ad_fmclidar1_ebz_zcu102 -adi_project_files ad_fmclidar1_ebz_zcu102 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] - -adi_project_run ad_fmclidar1_ebz_zcu102 diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_top.v b/projects/ad_fmclidar1_ebz/zcu102/system_top.v deleted file mode 100644 index 3be1ce737f8..00000000000 --- a/projects/ad_fmclidar1_ebz/zcu102/system_top.v +++ /dev/null @@ -1,234 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input [12:0] gpio_bd_i, - output [ 7:0] gpio_bd_o, - - input rx_ref_clk_p, - input rx_ref_clk_n, - input rx_device_clk_p, - input rx_device_clk_n, - output rx_sync0_p, - output rx_sync0_n, - output rx_sync1_p, - output rx_sync1_n, - input rx_sysref_p, - input rx_sysref_n, - input [ 3:0] rx_data_p, - input [ 3:0] rx_data_n, - - inout adc_fdb, - inout adc_fda, - inout adc_pdwn, - - // DAQ board's ADC SPI - - output spi_adc_csn, - output spi_adc_clk, - output spi_adc_mosi, - input spi_adc_miso, - - // DAQ board's clock chip - - output spi_clkgen_csn, - output spi_clkgen_clk, - output spi_clkgen_mosi, - input spi_clkgen_miso, - - // DAQ board's vco chip - - output spi_vco_csn, - output spi_vco_clk, - output spi_vco_mosi, - - // AFE board's DAC - - inout afe_dac_sda, - inout afe_dac_scl, - output afe_dac_clr_n, - output afe_dac_load, - - // AFE board's ADC - - output afe_adc_sclk, - output afe_adc_scn, - input afe_adc_sdi, - output afe_adc_convst, - - // Laser driver differential line - - output laser_driver_p, - output laser_driver_n, - - output laser_driver_en_n, - input laser_driver_otw_n, - - // GPIO's for the laser board - - inout [13:0] laser_gpio, - - // Vref selects for AFE board - - output [ 7:0] tia_chsel -); - - // internal signals - - wire [94:0] gpio_i; - wire [94:0] gpio_o; - wire [94:0] gpio_t; - wire rx_ref_clk; - wire rx_sync; - wire rx_sysref; - wire rx_device_clk; - wire rx_device_clk_ds; - wire laser_driver; - - // instantiations - - IBUFDS_GTE4 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - OBUFDS i_obufds_rx_sync0 ( - .I (rx_sync), - .O (rx_sync0_p), - .OB (rx_sync0_n)); - - OBUFDS i_obufds_rx_sync1 ( - .I (rx_sync), - .O (rx_sync1_p), - .OB (rx_sync1_n)); - - IBUFDS i_rx_device_clk_ds ( - .I (rx_device_clk_p), - .IB (rx_device_clk_n), - .O (rx_device_clk_ds)); - - BUFG i_rx_device_clk ( - .I (rx_device_clk_ds), - .O (rx_device_clk)); - - IBUFDS i_rx_sysref ( - .I (rx_sysref_p), - .IB (rx_sysref_n), - .O (rx_sysref)); - - // laser driver - - OBUFDS i_obufds_laser_driver ( - .I (laser_driver), - .O (laser_driver_p), - .OB (laser_driver_n)); - - // GPIO connections to the FMC connector - - ad_iobuf #( - .DATA_WIDTH(20) - ) i_fmc_iobuf ( - .dio_t ({gpio_t[51:38], 3'b0, gpio_t[34:32]}), - .dio_i ({gpio_o[51:32]}), - .dio_o ({gpio_i[51:32]}), - .dio_p ({ - laser_gpio, // 51:38 - afe_adc_convst, // 37 - output only - afe_dac_load, // 36 - output only - afe_dac_clr_n, // 35 - output only - adc_pdwn, // 34 - adc_fdb, // 33 - adc_fda // 32 - })); - - assign gpio_bd_o = gpio_o[ 7: 0]; - assign gpio_i[20: 8] = gpio_bd_i; - assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; - assign gpio_i[31:21] = gpio_o[31:21]; - assign gpio_i[94:52] = gpio_o[94:52]; - - // block design instance - - system_wrapper i_system_wrapper ( - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_data_2_n (rx_data_n[2]), - .rx_data_2_p (rx_data_p[2]), - .rx_data_3_n (rx_data_n[3]), - .rx_data_3_p (rx_data_p[3]), - .rx_ref_clk (rx_ref_clk), - .rx_device_clk (rx_device_clk), - .rx_sync_0 (rx_sync), - .rx_sysref_0 (rx_sysref), - .laser_driver (laser_driver), - .laser_driver_en_n (laser_driver_en_n), - .laser_driver_otw_n (laser_driver_otw_n), - .tia_chsel (tia_chsel), - .iic_dac_scl_io (afe_dac_scl), - .iic_dac_sda_io (afe_dac_sda), - .spi0_sclk (spi_adc_clk), - .spi0_csn (spi_adc_csn), - .spi0_miso (spi_adc_miso), - .spi0_mosi (spi_adc_mosi), - .spi1_sclk (spi_clkgen_clk), - .spi1_csn (spi_clkgen_csn), - .spi1_miso (spi_clkgen_miso), - .spi1_mosi (spi_clkgen_mosi), - .spi_vco_csn_i (1'b1), - .spi_vco_csn_o (spi_vco_csn), - .spi_vco_clk_i (1'b0), - .spi_vco_clk_o (spi_vco_clk), - .spi_vco_sdo_i (1'b0), - .spi_vco_sdo_o (spi_vco_mosi), - .spi_vco_sdi_i (1'b0), - .spi_afe_adc_csn_i (1'b1), - .spi_afe_adc_csn_o (afe_adc_scn), - .spi_afe_adc_clk_i (1'b0), - .spi_afe_adc_clk_o (afe_adc_sclk), - .spi_afe_adc_sdo_i (1'b0), - .spi_afe_adc_sdo_o (), - .spi_afe_adc_sdi_i (afe_adc_sdi)); - -endmodule