From 6167f1540b5327e024d16e116769999db7d70502 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 20 Sep 2022 13:19:05 +0100 Subject: [PATCH] ad7616_sdz/zc706: Update spi namings --- .../ad7616_sdz/zc706/serial_if_constr.xdc | 10 +++++----- projects/ad7616_sdz/zc706/system_bd.tcl | 8 ++++++++ projects/ad7616_sdz/zc706/system_top_pi.v | 2 +- projects/ad7616_sdz/zc706/system_top_si.v | 20 +++++++++---------- 4 files changed, 24 insertions(+), 16 deletions(-) diff --git a/projects/ad7616_sdz/zc706/serial_if_constr.xdc b/projects/ad7616_sdz/zc706/serial_if_constr.xdc index b9e6cb514b..88705f2086 100644 --- a/projects/ad7616_sdz/zc706/serial_if_constr.xdc +++ b/projects/ad7616_sdz/zc706/serial_if_constr.xdc @@ -3,11 +3,11 @@ # data interface -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs_n] ; ## FMC_LPC_LA04_N # control lines diff --git a/projects/ad7616_sdz/zc706/system_bd.tcl b/projects/ad7616_sdz/zc706/system_bd.tcl index caa1a536cc..12a7c35a38 100644 --- a/projects/ad7616_sdz/zc706/system_bd.tcl +++ b/projects/ad7616_sdz/zc706/system_bd.tcl @@ -9,5 +9,13 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file +# system level parameters +set SI_OR_PI $ad_project_params(SI_OR_PI) + +adi_project_files ad7616_sdz_zc706 [list \ + "../../../library/common/ad_edge_detect.v" \ + "../../../library/util_cdc/sync_bits.v" \ + ] + source ../common/ad7616_bd.tcl diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v index d12861e9fe..df81ed4ec9 100644 --- a/projects/ad7616_sdz/zc706/system_top_pi.v +++ b/projects/ad7616_sdz/zc706/system_top_pi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v index 0a79d59b0f..e5cb62de9f 100644 --- a/projects/ad7616_sdz/zc706/system_top_si.v +++ b/projects/ad7616_sdz/zc706/system_top_si.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -73,10 +73,10 @@ module system_top ( inout iic_scl, inout iic_sda, - output spi_sclk, - output spi_sdo, - input [ 1:0] spi_sdi, - output spi_cs_n, + output ad7616_spi_sclk, + output ad7616_spi_sdo, + input [ 1:0] ad7616_spi_sdi, + output ad7616_spi_cs_n, output adc_reset_n, output adc_convst, @@ -152,11 +152,11 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .spdif (spdif), - .rx_sclk (spi_sclk), - .rx_sdo (spi_sdo), - .rx_sdi (spi_sdi), - .rx_cnvst (adc_convst), - .rx_cs_n (spi_cs_n), + .ad7616_spi_sdo (ad7616_spi_sdo), + .ad7616_spi_sdi (ad7616_spi_sdi), + .ad7616_spi_cs (ad7616_spi_cs), + .ad7616_spi_sclk (ad7616_spi_sclk), + .rx_cnvst (adc_cnvst), .rx_busy (adc_busy)); endmodule