@@ -382,11 +382,15 @@ int MXC_UART_RevB_AbortTransmission(mxc_uart_revb_regs_t *uart)
382382 MXC_UART_ClearTXFIFO ((mxc_uart_regs_t * )uart );
383383 int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t * )uart );
384384
385+ MXC_UART_RevB_AsyncStop (uart );
386+
385387 if (states [uart_num ].channelTx >= 0 ) {
386388 MXC_DMA_Stop (states [uart_num ].channelTx );
389+ MXC_UART_RevB_DMACallback (states [uart_num ].channelTx , E_ABORT );
387390 }
388391 if (states [uart_num ].channelRx >= 0 ) {
389392 MXC_DMA_Stop (states [uart_num ].channelRx );
393+ MXC_UART_RevB_DMACallback (states [uart_num ].channelRx , E_ABORT );
390394 }
391395
392396 if (states [uart_num ].auto_dma_handlers ) {
@@ -1121,6 +1125,9 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma)
11211125 MXC_DMA_Init ();
11221126#endif
11231127
1128+ // All error interrupts are related to RX
1129+ MXC_UART_EnableInt ((mxc_uart_regs_t * )(req -> uart ), MXC_UART_REVB_ERRINT_EN );
1130+
11241131 // Reset rx/tx counters,
11251132 req -> rxCnt = 0 ;
11261133 req -> txCnt = 0 ;
@@ -1182,7 +1189,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error)
11821189 /* Only call TX callback if RX component is complete/disabled. Note that
11831190 we are checking the request associated with the _channel_ assignment, not
11841191 the other side of the state struct. */
1185- temp_req -> callback ((mxc_uart_req_t * )temp_req , E_NO_ERROR );
1192+ temp_req -> callback ((mxc_uart_req_t * )temp_req , error );
11861193 }
11871194 break ;
11881195 } else if (states [i ].channelRx == ch ) {
@@ -1197,7 +1204,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error)
11971204 if (temp_req -> callback != NULL &&
11981205 ((states [i ].rx_req -> txCnt == states [i ].rx_req -> txLen ) ||
11991206 states [i ].rx_req -> txData == NULL )) {
1200- temp_req -> callback ((mxc_uart_req_t * )temp_req , E_NO_ERROR );
1207+ temp_req -> callback ((mxc_uart_req_t * )temp_req , error );
12011208 }
12021209 break ;
12031210 }
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