MAX78002 SDHC Raw example sets SD clock incorrectly.

[jasonwagar]

The SD card clock is tapped directly from the 120MHz internal primary oscillator. There is clock divider with divide by 2 and divide by 4 options. This should always be set to divide by 4 to keep the clock below the 52MHz max for eMMC. In the current code the divider is configured based on the system clock, which is unrelated to the SD clock.

[Jake-Carter]

Thanks @jasonwagar, I've opened the PR above with the fix.

You should now be able to specify the exact clock frequency you want with the SDHC_CLK_FREQ build variable.

I'm seeing some SDHC_Raw issues with the multi-block test code at 20Mhz with SDHC_CLK_FREQ = 20000000...

***** MAX78002 SDHC Example *****
Waiting for card.
Card inserted.
Card Initialized.
Card type: SDHC
--> 1-bit data bus example <--
blocking read/write ok
Passed blocking
blocking erase ok
blocking erase read ok
Passed erase
non-blocking write ok
non-blocking read ok
Passed async
--> 4-bit data bus example <--
blocking read/write ok
Passed blocking
blocking erase ok
blocking erase read ok
Passed erase
non-blocking write ok
non-blocking read ok
Passed async
--> Blocking, 4-bit data bus, multi-block example <--
data compare failed
 FAIL 

Example Failed

but at 10Mhz they pass...

***** MAX78002 SDHC Example *****
Waiting for card.
Card inserted.
Card Initialized.
Card type: SDHC
--> 1-bit data bus example <--
blocking read/write ok
Passed blocking
blocking erase ok
blocking erase read ok
Passed erase
non-blocking write ok
non-blocking read ok
Passed async
--> 4-bit data bus example <--
blocking read/write ok
Passed blocking
blocking erase ok
blocking erase read ok
Passed erase
non-blocking write ok
non-blocking read ok
Passed async
--> Blocking, 4-bit data bus, multi-block example <--
 PASS 

Example Succeeded

I can run the (updated) SDHC_FAT example just fine at 30Mhz off the ISO, and 60Mhz off the IPO. Is the FAT format suitable for your application? Or do you want to use the raw data?