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VGA_example.xpr
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VGA_example.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2015.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="10" Path="C:/Xilinx/Projects/VGA_example/VGA_example.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="a84240f0da07429aa15f3c7e4fe2ea09"/>
<Option Name="Part" Val="xc7z010clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../xilinx/projects/ip_repo/vga_1.0"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/VGA_example.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/VGA_example.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/BoardDesign_0/BoardDesign_0.bd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../example_design/example_design.srcs/sources_1/bd/BoardDesign_0/BoardDesign_0.bd"/>
<Attr Name="ImportTime" Val="1446500905"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_auto_pc_0/BoardDesign_0_auto_pc_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconcat_0_1/BoardDesign_0_xlconcat_0_1.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconstant_0_1/BoardDesign_0_xlconstant_0_1.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconstant_0_0/BoardDesign_0_xlconstant_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconcat_0_0/BoardDesign_0_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_processing_system7_0_0/BoardDesign_0_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_proc_sys_reset_0_0/BoardDesign_0_proc_sys_reset_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_axi_interconnect_1_0/BoardDesign_0_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_axi_interconnect_0_0/BoardDesign_0_axi_interconnect_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_VGA_0_0/BoardDesign_0_VGA_0_0.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconcat_0_2/BoardDesign_0_xlconcat_0_2.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_xlconstant_0_2/BoardDesign_0_xlconstant_0_2.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="ip/BoardDesign_0_auto_pc_1/BoardDesign_0_auto_pc_1.xci"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="hw_handoff/BoardDesign_0_bd.tcl"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="hw_handoff/BoardDesign_0.hwh"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="hdl/BoardDesign_0.hwdef"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="BoardDesign_0_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="BoardDesign_0.bd" FileRelPathName="hdl/BoardDesign_0.v"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/BoardDesign_0/hdl/BoardDesign_0_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/BoardDesign_0/ip/BoardDesign_0_VGA_0_0/BoardDesign_0_VGA_0_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/BoardDesign_0/ip/BoardDesign_0_VGA_0_0/src/blk_mem_gen_pixel/blk_mem_gen_pixel.upgrade_log"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="BoardDesign_0_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/Projects/ZYBO_Master.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../example_design/example_design.srcs/constrs_1/imports/Projects/ZYBO_Master.xdc"/>
<Attr Name="ImportTime" Val="1446498569"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="BoardDesign_0_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>