From cea489ecf68de5e5b5744f732b5bff03c48f4cf2 Mon Sep 17 00:00:00 2001 From: Patrick Jattke Date: Thu, 25 Jan 2024 01:23:28 +0100 Subject: [PATCH] docs: adds details about DDR5 simulation --- docs/source/ddr5_tester.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/source/ddr5_tester.md b/docs/source/ddr5_tester.md index 9aa69603d..0f349de3e 100644 --- a/docs/source/ddr5_tester.md +++ b/docs/source/ddr5_tester.md @@ -286,3 +286,13 @@ buildroot login: root login[65]: root login on 'console' ``` + +## Simulation + +The simulation is based on a DDR5 DRAM model ([sdram_simulation_model.py](../../third_party/litedram/litedram/phy/ddr5/sdram_simulation_model.py)) and a DDR5 PHY simulation model ([simphy.py](../../third_party/litedram/litedram/phy/ddr5/simphy.py)). These two models are used by the SoC simulation model ([simsoc.py](../../third_party/litedram/litedram/phy/ddr5/simsoc.py)). + +The simulation can be started with: + +```sh +python3 third_party/litedram/litedram/phy/ddr5/simsoc.py --no-masked-write --with-sub-channels --dq-dqs-ratio 4 --modules-in-rank 1 --log-level error --skip-csca --skip-reset-seq --skip-mrs-seq --with-prompt --l2-size 256 --uart-name serial +```