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spi: master doesn't transfer 2 MSB in data byte #84
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It also drops the 2 MSB in the command byte. |
olajep
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Use oh_fifo_cdc for XILINX target. oh_fifo_sync does work in simulation but it does not work when synthesizing in Vivado (see aolofsson#84). This also includes a hack that forces the FIFO depth/width to 32/104 when TARGET is set to "XILINX" (only available FIFO IP atm.). Signed-off-by: Ola Jeppsson <[email protected]>
olajep
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May 27, 2016
Use oh_fifo_cdc for XILINX target. oh_fifo_sync does work in simulation but it does not work when synthesizing in Vivado (see aolofsson#84). This also includes a hack that forces the FIFO depth/width to 32/104 when TARGET is set to "XILINX" (only available FIFO IP atm.). Signed-off-by: Ola Jeppsson <[email protected]>
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olajep
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May 29, 2016
Use oh_fifo_cdc for XILINX target. oh_fifo_sync does work in simulation but it does not work when synthesizing in Vivado (see aolofsson#84). This also includes a hack that forces the FIFO depth/width to 32/104 when TARGET is set to "XILINX" (only available FIFO IP atm.). Signed-off-by: Ola Jeppsson <[email protected]>
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Test case:
fclk0 = 25 MHz clkdiv=254 sclk = 100 kHz
As seen in the waveform capture master does not transfer the two most significant bits in the data byte.
This does not seem to happen in simulation.
waveform.vcd.txt
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