braindrop_nativelink_simulation.rpt

Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  arria10
Quartus root          :  c:/intelfpga/17.0/quartus/bin64/
Quartus sim root      :  c:/intelfpga/17.0/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation\modelsim

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Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga/17.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File braindrop_run_msim_rtl_verilog.do already exists - backing up current file as braindrop_run_msim_rtl_verilog.do.bak5
Info: Spawning ModelSim-Altera Simulation software 
Info: NativeLink simulation flow was successful