Switch atomic-polyfill to portable-atomic

Author: jbeaurivage

hal/Cargo.toml

@@ -31,7 +31,6 @@ features = ["samd21g", "samd21g-rt", "unproven", "usb"]
 
 [dependencies]
 aes = "0.7.5"
-atomic-polyfill = "0.1.8"
 bitfield = "0.13"
 bitflags = "1.2.1"
 cipher = "0.3"
@@ -43,6 +42,7 @@ nb = "1.0"
 num-traits = {version = "0.2.14", default-features = false}
 opaque-debug = "0.3.0"
 paste = "1.0.11"
+portable-atomic = {version = "1.5.0", optional = true, default-features = false}
 rand_core = "0.6"
 seq-macro = "0.3"
 typenum = "1.12.0"
@@ -97,9 +97,6 @@ atsame53n = {version = "0.13.0", path = "../pac/atsame53n", optional = true}
 atsame54n = {version = "0.13.0", path = "../pac/atsame54n", optional = true}
 atsame54p = {version = "0.13.0", path = "../pac/atsame54p", optional = true}
 
-
-
-
 #===============================================================================
 # Features
 #===============================================================================
@@ -201,6 +198,7 @@ async = [
     "embassy-sync",
     "embedded-hal-async",
     "futures",
+    "portable-atomic"
 ]
 
 #===============================================================================

hal/src/async_hal/timer.rs

@@ -1,5 +1,4 @@
 use crate::{ehal::timer::CountDown, timer_traits::InterruptDrivenTimer, typelevel::Sealed};
-use atomic_polyfill::AtomicBool;
 use core::{
     future::poll_fn,
     sync::atomic::Ordering,
@@ -9,6 +8,7 @@ use cortex_m::interrupt::InterruptNumber;
 use cortex_m_interrupt::NvicInterruptRegistration;
 use embassy_sync::waitqueue::AtomicWaker;
 use fugit::{MicrosDurationU32, MillisDurationU32, NanosDurationU32};
+use portable_atomic::AtomicBool;
 
 #[cfg(feature = "thumbv6")]
 use crate::thumbv6m::timer;

hal/src/dmac/channel/mod.rs

@@ -264,6 +264,7 @@ impl<Id: ChId, S: Status> Channel<Id, S> {
     }
 
     /// Stop transfer on channel whether or not the transfer has completed
+    #[inline]
     pub(crate) fn stop(&mut self) {
         self.regs.chctrla.modify(|_, w| w.enable().clear_bit());
     }
@@ -274,10 +275,12 @@ impl<Id: ChId, S: Status> Channel<Id, S> {
         !self.regs.chctrla.read().enable().bit_is_set()
     }
 
-    /// Returns whether the transfer's success status.
+    /// Returns the transfer's success status.
+    #[allow(dead_code)]
+    #[inline]
     pub(crate) fn xfer_success(&mut self) -> super::Result<()> {
-        let is_ok = self.regs.chintflag.read().terr().bit_is_clear();
-        is_ok.then_some(()).ok_or(super::Error::TransferError)
+        let success = self.regs.chintflag.read().terr().bit_is_clear();
+        success.then_some(()).ok_or(super::Error::TransferError)
     }
 }
 

hal/src/dmac/dma_controller.rs

@@ -335,6 +335,7 @@ impl DmaController {
     with_num_channels!(define_split);
 }
 
+#[cfg(feature = "async")]
 macro_rules! define_split_future {
     ($num_channels:literal) => {
         seq!(N in 0..$num_channels {

hal/src/sercom/i2c/flags.rs

@@ -85,6 +85,7 @@ pub enum Error {
     Dma(crate::dmac::Error),
 }
 
+#[cfg(feature = "async")]
 impl embedded_hal_async::i2c::Error for Error {
     // _ pattern reachable when "dma" feature enabled.
     #[allow(unreachable_patterns)]

hal/src/sercom/spi.rs

@@ -417,6 +417,7 @@ bitflags! {
     }
 }
 
+#[allow(dead_code)]
 impl Flags {
     pub(super) const RX: Self = unsafe { Self::from_bits_unchecked(RX_FLAG_MASK) };
     pub(super) const TX: Self = unsafe { Self::from_bits_unchecked(TX_FLAG_MASK) };