Fix some errors when merging master

Author: jbeaurivage

Diff for: hal/src/dmac/dma_controller.rs

@@ -148,50 +148,6 @@ pub struct RoundRobinMask {
 }
 
 impl<T> DmaController<T> {
-    /// Initialize the DMAC and return a DmaController object useable by
-    /// [`Transfer`](super::transfer::Transfer)'s. By default, all
-    /// priority levels are enabled unless subsequently disabled using the
-    /// `level_x_enabled` methods.
-    #[inline]
-    pub fn init(mut dmac: DMAC, _pm: &mut PM) -> Self {
-        // ----- Initialize clocking ----- //
-        #[cfg(feature = "thumbv6")]
-        {
-            // Enable clocking
-            _pm.ahbmask.modify(|_, w| w.dmac_().set_bit());
-            _pm.apbbmask.modify(|_, w| w.dmac_().set_bit());
-        }
-
-        Self::swreset(&mut dmac);
-
-        // SAFETY this is safe because we write a whole u32 to 32-bit registers,
-        // and the descriptor array addesses will never change since they are static.
-        // We just need to ensure the writeback and descriptor_section addresses
-        // are valid.
-        unsafe {
-            dmac.baseaddr
-                .write(|w| w.baseaddr().bits(DESCRIPTOR_SECTION.as_ptr() as u32));
-            dmac.wrbaddr
-                .write(|w| w.wrbaddr().bits(WRITEBACK.as_ptr() as u32));
-        }
-
-        // ----- Select priority levels ----- //
-        dmac.ctrl.modify(|_, w| {
-            w.lvlen3().set_bit();
-            w.lvlen2().set_bit();
-            w.lvlen1().set_bit();
-            w.lvlen0().set_bit()
-        });
-
-        // Enable DMA controller
-        dmac.ctrl.modify(|_, w| w.dmaenable().set_bit());
-
-        Self {
-            dmac,
-            _interrupts: NoneT,
-        }
-    }
-
     /// Enable multiple priority levels simultaneously
     #[inline]
     pub fn enable_levels(&mut self, mask: PriorityLevelMask) {
@@ -264,15 +220,15 @@ impl<T> DmaController<T> {
     }
 }
 
-impl DmaController<NoneT> {
+impl DmaController {
     /// Initialize the DMAC and return a DmaController object useable by
     /// [`Transfer`](super::transfer::Transfer)'s. By default, all
     /// priority levels are enabled unless subsequently disabled using the
     /// `level_x_enabled` methods.
     #[inline]
     pub fn init(mut dmac: DMAC, _pm: &mut PM) -> Self {
         // ----- Initialize clocking ----- //
-        #[cfg(any(feature = "samd11", feature = "samd21"))]
+        #[cfg(feature = "thumbv6")]
         {
             // Enable clocking
             _pm.ahbmask.modify(|_, w| w.dmac_().set_bit());

Diff for: hal/src/lib.rs

@@ -90,7 +90,6 @@ pub use async_hal::*;
 #[cfg(feature = "async")]
 pub use cortex_m_interrupt::{self, take_exception, take_nvic_interrupt};
 
-#[cfg(all(feature = "unproven", feature = "dma"))]
 #[cfg(feature = "dma")]
 pub mod dmac;
 

Diff for: hal/src/thumbv6m/eic/pin.rs

@@ -9,8 +9,6 @@ use crate::{
 };
 use core::mem::ManuallyDrop;
 
-use super::EIC;
-
 /// The EicPin trait makes it more ergonomic to convert a gpio pin into an EIC
 /// pin. You should not implement this trait for yourself; only the
 /// implementations in the EIC module make sense.
@@ -158,10 +156,6 @@ crate::paste::item! {
                 }
             });
         }
-
-        fn id(&self) -> ExternalInterruptID {
-            $num
-        }
     }
 
     #[cfg(feature = "async")]
@@ -324,6 +318,9 @@ crate::paste::item! {
 
 // SAMD11
 
+#[cfg(feature = "samd11")]
+pub const NUM_CHANNELS: usize = 8;
+
 #[cfg(feature = "samd11")]
 mod impls {
     use super::*;
@@ -359,11 +356,11 @@ mod impls {
     });
 }
 
-#[cfg(feature = "samd11")]
-pub const NUM_CHANNELS: usize = 8;
-
 // SAMD21
 
+#[cfg(feature = "samd21")]
+pub const NUM_CHANNELS: usize = 16;
+
 #[cfg(feature = "samd21")]
 mod impls {
     use super::*;

Diff for: hal/src/thumbv7em/eic/pin.rs

@@ -169,10 +169,6 @@ crate::paste::item! {
             });
         }
 
-        fn id(&self) -> ExternalInterruptID {
-            $num
-        }
-
         /// Turn an EIC pin into a pin usable as a [`Future`](core::future::Future).
         /// The correct interrupt source is needed.
         #[cfg(feature = "async")]