COE files in block design use absolute paths

[LRitzdorf]

I'm using vivado-git with a block design project that includes several BRAM modules, each of which has an associated COE file to set its contents. When calling wproj to generate a project TCL script, the absolute paths of these COE files are kept, instead of being replaced with relative ones. Here's an example snippet, for reference:

  # Create instance: blk_mem_gen_1, and set properties
  set blk_mem_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_1 ]
  set_property -dict [list \
    CONFIG.Coe_File {c:/<project path>/src/design/coe/ram_init_1_1.coe} \
    CONFIG.Enable_32bit_Address {false} \
    <...more properties, trimmed for brevity>
  ] $blk_mem_gen_1

Does Vivado even support using relative paths here? If so, can that be implemented as part of this project, or is it preferable to just type the relative path into Vivado in the first place?

[LRitzdorf]

Looks like relative paths are possible, if we pass $origin_dir into the procedure that creates the BD. Vivado will throw an [INFO] message for each one, since it internally converts absolute paths to relative ones, but that should be fine.

(Incidentally, the relative paths it comes up with are horrendous — at least in my case, they used ../ to ascend all the way to the C drive, then re-traversed back down into the same directory they started in.)