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3. Day 3 - Advanced Constraints
- 3.1. Clock Tree Modelling - Uncertainty
- 3.2. Loading Design get_cells, get_ports, get_nets
- 3.3. Loading Design get_pins, get_clocks, querying_clocks
- 3.4 Creating Clock Waveforms
- 3.5 Clock Network Modelling - Uncertainty, report_timing
- 3.6 IO Delays
- 3.7 SDC generated_clk
- 3.8 SDC vclk, max_latency, rise_fall IODelays
Design Compiler is an Advanced Synthesis Tool used by leading semiconductor companies across world.
Synthesis of logic circuits plays a crucial role in optimizing the logic and achieving the targeted performance, area and power goals of an IC.
Understanding the fundamentals of design are very important to give the correct inputs to the tool to achieve the best-in-class netlist quality.
This workshop explores the following aspects,
- Design fundamentals
- Setting up DC for synthesis
- Understanding STA
- Understanding and writing the Synopsys Design Constraints [SDC].
- Analyzing the quality of netlist synthesized.
Design Compiler RTL synthesis solution enables users to meet today's design challenges with concurrent optimization of timing, area, power and test. Design Compiler includes innovative topographical technology that enables a predictable flow resulting in faster time to results.
Benefits:
- Concurrent optimization of timing, area, power and test
- Results correlate within 10% of physical implementation
- Removes timing bottlenecks by creating fast critical paths
- Gate-to-gate optimization for smaller area on new or legacy designs while maintaining timing Quality of Results (QoR)
- Cross-probing between RTL, schematic, and timing reports for fast debug
- Offers more flexibility for users to control optimization on specific areas of designs
- Enables higher efficiency with integrated static timing analysis, test synthesis and power synthesis
- Support for multi voltage and multi supply
- 2X faster runtime on quad-core compute servers
SDC The Synopsys Design Constraints (SDC) format is used to specify the design intent, including timing, power and area constraints for a design. This format is used by different EDA tools to synthesize and analyse a design.SDC file syntax is based on TCL format and all commands of sdc file follow the TCL syntax. DC Setup
//create a directory
$ mkdir DC_WORKSHOP
//Git Clone sky130RTLDesignAndSynthesisWorkshop.
$ git clone https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git
This is for a 130nm file, but we will be using SAED 32nm EDK's CCS model's .lib/.db file
$ gedit /home/bharath/DC_WORKSHOP_/DC_WORKSHOP/verilog_files/lab1_flop_with_en.v
$ gedit /home/bharath/DC_WORKSHOP_/DC_WORKSHOP/verilog_files/tb_lab1_flop_with_en.v
.lib file is a collection of logical modules which includes all basic logic gates. It may also contain different flavors of the same gate (2 input AND, 3 input AND – slow, medium and fast version).
A cell delay in the digital logic circuit depends on the load of the circuit which here is Capacitance.
Faster the charging / discharging of the capacitance --> Lesser is the Cell Delay
Inorder to charge/discharge the capacitance faster, we use wider transistors that can source more current. This will help us reduce the cell delay but at the same time, wider transistors consumer more power and area. Similarly, using narrower transistors help in reduced area and power but the circuit will have a higher cell delay. Hence, we have to compromise on area and power if we are to design a circuit with low cell delay.
A Constraint is a guidance file given to a synthesizer inorder to enable an optimum implementation of the logic circuit by selecting the appropriate flavour of cells (fast or slow).
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
We need to keep basic timing requiremets such as setup-time and holf-time, such that the flops in the design don't get into metastability . Metastabiltiy means a unknown value at the output of some intermediate flop and cause the whole design to go haywire
Clock A clock signal oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock signal is produced by a clock generator.
Clock uncertainty is the difference between the arrivals of clocks at registers in one clock domain or between domains. it can be classified as static and dynamic clock uncertainties.
Timing Uncertainty of clock period is set by the command set_clock_uncertainty at the synthesis stage to reserve some part of the clock period for uncertain factors (like skew, jitter, OCV, CROSS TALK, MARGIN or any other pessimism) which will occur in PNR stage. The uncertainty can be used to model various factors that can reduce the clock period. It can define for both setup and hold.
$ report_timing -to REGC_reg/D -delay min
$ report_timing -to REGC_reg/D -delay max
$ set_input_delay -max 5 -clock [get_clocks myclk] [get_ports IN_A]
$set_input_delay -max 5 -clock [get_clocks myclk] [get_ports IN_B]
$report_port -verbose
$ set_input_delay -min 1 -clock [get_clocks myclk] [get_ports IN_A]
$set_input_delay -min 1 -clock [get_clocks myclk] [get_ports IN_B]
$report_timing -from IN_A -trans -nosplit
$ set_input_delay -max 5 -clock [get_clocks myclk] [get_ports OUT_Y]
$set_input_delay -min 1 -clock [get_clocks myclk] [get_ports OUT_Y]
$report_timing -from OUT_Y -trans -nosplit
$ set_load -max 0.4 [get_ports OUT_Y]
$report_timing -to OUT_Y -cap -trans -nosplit
$ set_load -min 0.1 [get_ports OUT_Y]
$report_timing -to OUT_Y -cap -trans -nosplit -delay min
$ create_generated_clock -source reference_pin [-divide_by divide_factor] [-multiply_by multiply_factor] [-invert] source
Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.
The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.
$ create_generated_clock -name MYGEN_CLK -master myclk -source [get_ports clk] -div 1 [get_ports out_clk]
$report_clocks *
A virtual clock is used as a reference to constrain the interface pins by relating the arrivals at input/output ports with respect to it with the help of input and output delays.
$ create_clock –name VCLK –period 10
It specifies the drive characteristics of input or inout ports that are driven by the cells in the technology library. These commands associate a library pin with input ports so that delay calculation can be accurately modelled.
- VCLK
$ create_clock -name MYCLK -per 10
The combinational optimization phase transforms the logic-level description of the combinational logic to a gate-level netlist. Combinational optimization includes
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Technology-Independent Optimization This optimization operates at the logic level. Design Compiler represents the gates as a set of Boolean logic equations.
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Mapping During this process, Design Compiler selects components from the logic library to implement the logic structure.
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Technology-Specific Optimization This optimization operates at the gate level.
Sequential optimization includes the initial optimization phase, which maps sequential cells to cells in the library, and the final optimization phase, where Design Compiler optimizes timing-critical sequential cells (cells on the critical path):
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Initial Sequential Optimization
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Final Sequential Optimization
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$ set_boundary_optimization u_im false
$set_multicycle_path -setup 2 -to prod_reg[*]/D -from [all_inputs]
$set_multicycle_path -hold 1 -to prod_reg[*]/D -from [all_inputs]
- Kunal Ghosh, Co-Founder (VLSI SYSTEM DESIGN - VSD)
- https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/?q=%2Frtl-design-using-verilog-with-sky130-technology%2F&v=a98eef2a3105
- https://github.com/kunalg123/vsdflow
- https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop
- https://github.com/google/skywater-pdk
- https://allaboutfpga.com/setup-time-and-hold-time-in-fpga/