- Tool used
- Overview
- NMOS- Basic element in circuit design
- Regions of operation of NMOS
- Introduction to spice
- CMOS
- Acknowlegement
The Synopsys Custom Compiler™ design environment is a modern solution for full-custom analog, custom digital, and mixed-signal IC design. As the heart of the Synopsys Custom Design Platform, Custom Compiler provides design entry, simulation management and analysis, and custom layout editing features. It delivers industry-leading productivity, performance, and ease-of-use while remaining easy to adopt for users of legacy tools.
we will be Starting form the concepts of basic element in cicuit design NMOS, its characteristics curve IDVgs, IDVds, its regions of operation - drain current equation, threshold voltage equation, effect of long channel and short channel device (velocity saturation)on the behavioral characteristic of NMOS. Spice scripting and simulation of the learned concept gives a more practical analysis of its characteritics. CMOS inverter circuits its design consideration is learned and simulated including its voltage transfer characteristics, static behaviour evaluation defining its robustness based on the 4 parameters viz switching threshold voltage (Vm), noise magin, power supply variation and device variation. Also the dynamic characteristics – propagation delay of the CMOS is learned and simulated. The importance of the transistor sizes while designing a CMOS inverter for a particular application is seen. All the above design consideration assist in finding the delay table and noise margin for different transistor sizes which can be compared with the actual values provided by the particular pdk. This workshop gives a detail understanding on the basic building block of the VLSI design – CMOS.
.param vds=1.8 vgs=1.8
.option PARHIER = LOCAL
.option PORT_VOLTAGE_SCALE_TO_2X = 1
.option RUNLVL = 3
.option WDF=1
.temp 25
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09-SP2
*Sun Apr 17 10:53:39 2022
.global gnd!
********************************************************************************
* Library : mos_testing
* Cell : nmos4t_hvt_iv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm0 net1 net4 gnd! gnd! n105_hvt w=0.1u l=0.03u nf=1 m=1
v4 net7 gnd! dc='vgs'
v1 net1 gnd! dc='vds'
r3 net7 net4 r=1k
.dc v4 0 1.8 .02
.option opfile=1 split_dp=1
.option probe=1
.probe dc v(*) level=1
.probe dc isub(xm0.1)
.end
The pictorial representation of an NMOS device with its various terminals is as shown in figure below. Is consist of the followng
- 4 terminal device - drain(D), gate(G), source(S), body(B)
- Ptype substrate
- Consist of Isolation region (Si02)
- n+ drain and source terminal
- Gate oxide
- PolySi or metal gate – drives the nmos
There are three regions of operation in NMOS transistor. In each of the region The drain current (ID) changes with respect to the gate to source voltage (Vgs) and drain to source voltage(Vds). When Vsb = 0
- Initiallly Gate voltage, source voltage and drain voltage is at zero Volt.
- The source substrate and drain substrate reqion forms a pn juction diode and both the jucnction are off as no voltage is applied to the drain and source terminal,
- A high resistance area is formed between the source and the drain. Now
- When the Vgs voltage is increased a positive charge is formed at the gate terminal which repels the positive charge of the p type substrate from the substrate which leaves negative charge at the surface.
- Vgs is further increase more and more positive charge of the ptype substrate repels resulting in depletion region.
- the semiconductor surface inverts to n type material and the phenomenon is known as strong inversion.
The gate to source voltage at which the strong inversion occurs is known as “Threshold voltage".
When Vsb = +ve voltage
- The formation of the channel (strong inversion at the surface) is delayed as compared to when Vsb is 0.
- n+ and the p substrate forms depletion region across the source substrate and drain substarte junction
- Width of the depletion region more towards the source substrate junction
- More gate to source voltage Vgs required for strong inversion to occur
Threshold voltage:
All the above parameter are manufacturing process parameters, given by the foundry.
In this region the gate to source voltage Vgs is less than the threshold voltage and thus no channel appears between the source and the drain region indicating a high resistance area between the source and the drain. Hence, the drain current is zero.
For cut off, 0 < Vgs < Vth
ID = 0
- When Vgs voltage is higher than threshold voltage Vt, the voltage difference results in induce charges across the semiconductor surface (channel)
- The change in voltage is basically proportional to the change in the channel width
- When a small voltage is be appiled across the Vds a voltage gradient appears acorss the channel as Vbs is 0V and Vds is = some voltage
- The effective length (after inversion) L of the channel is less than the actual length which occurs due to the fabrication process
- V(x) is the voltage at the point x along the width of the channel as shown in the figure below
Drift current for resistive mode of operation
- When (Vgs - Vds) >= Vt, the transistor is said to be in saturation region
- The voltage at which the difference in (Vgs - Vds) = Vt, pinch off condition is said to occur
- From the pinch off condition and further rise in threshold voltage, the channel near the drain region slowly starts disappearing as the required condition - strong inversion is violated
- The drain current in saturation region is given as
The figure below shows the drain current of both linear and saturation region with varying Vds.
The following set of programs are wriiten to generate the ID-VDs, ID-Vgs curve of different transistor sizes using SAED-32/28nm TT corner.
1a. Spice deck for w=5u L=2u and generate ID-VDS graph
Spice deck to generate the ID-Vds curve of a NMOS transistor using sky130 technology
*Model Description
.option search='/home/skandha/Tools_SNPS/Downloads_temp/SAED32nm_PDK_09302020/hspice'
.param vds=1.8 vgs=1.8
.option PARHIER = LOCAL
.option PORT_VOLTAGE_SCALE_TO_2X = 1
.option RUNLVL = 3
.option WDF=1
.temp 25
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09-SP2
*Sat Apr 30 02:31:39 2022
.global gnd!
********************************************************************************
* Library : mos_testing
* Cell : nmos4t_hvt_iv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm0 net1 net4 gnd! gnd! n105_hvt w=0.2u l=0.1u nf=1 m=1
v4 net7 gnd! dc='vgs'
v1 net1 gnd! dc='vds'
r3 net7 net4 r=1k
.dc vds 0 1.8 .02
.option opfile=1 split_dp=1
.option probe=1
.probe dc v(*) level=1
.probe dc isub(xm0.1)
.end
1b. Spice deck for w=1u L=0.5u to generate Id-Vgs curve
*Model Description
option search='/home/skandha/Tools_SNPS/Downloads_temp/SAED32nm_PDK_09302020/hspice'
.param vds=1.8 vgs=1.8
.option PARHIER = LOCAL
.option PORT_VOLTAGE_SCALE_TO_2X = 1
.option RUNLVL = 3
.option WDF=1
.temp 25
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09-SP2
*Sat Apr 30 02:17:42 2022
.global gnd!
********************************************************************************
* Library : mos_testing
* Cell : nmos4t_hvt_iv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm0 net1 net4 gnd! gnd! n105_hvt w=1u l=0.5u nf=1 m=1
v4 net7 gnd! dc='vgs'
v1 net1 gnd! dc='vds'
r3 net7 net4 r=1k
.dc vgs 0 1.8 .02
.option opfile=1 split_dp=1
.option probe=1
.probe dc v(*) level=1
.probe dc isub(xm0.1)
.end
This is one of the effect for short channel. Conventionally there are three mode of operation of mosfet viz cut off, linear and saturation region, however for lower nodes there are four mode of operation with velocity saturation region being one apart from the other three. In velocity saturation effect it is observe that for lower value of electric field the velocity is linear however after a certain time or higher electric field the velocity starts to saturate or becomes constant due to an effect known as scattering effect.
Let us now see the effect of velocity saturation on the drain current equation.
- Current should increase at lower nodes as shown in above equation
- However velocity saturation causes the device to saturate early
The below program shows the effect of velocity saturation on the lower node devices
2a. Spice deck for w=0.1u L=0.05u and generate ID-VDS graph
Spice deck for w=0.39u L=0.15u and generate ID-VDS graph
*Model description
.option search='/home/skandha/Tools_SNPS/Downloads_temp/SAED32nm_PDK_09302020/hspice'
.param vds=1.8 vgs=1.8
.option PARHIER = LOCAL
.option PORT_VOLTAGE_SCALE_TO_2X = 1
.option RUNLVL = 3
.option WDF=1
.temp 25
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09-SP2
*Sat Apr 30 02:35:52 2022
.global gnd!
********************************************************************************
* Library : mos_testing
* Cell : nmos4t_hvt_iv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm0 net1 net4 gnd! gnd! n105_hvt w=0.1u l=0.05u nf=1 m=1
v4 net7 gnd! dc='vgs'
v1 net1 gnd! dc='vds'
r3 net7 net4 r=1k
.dc vds 0 1.8 .02
.option opfile=1 split_dp=1
.option probe=1
.probe dc v(*) level=1
.probe dc isub(xm0.1)
.end
2b. Spice deck for w=0.1u and l=0.05u to generate Id-Vgs curve
Spice deck for w=0.39u and l=0.15u to generate Id-Vgs curve
*Model description
.option search='/home/skandha/Tools_SNPS/Downloads_temp/SAED32nm_PDK_09302020/hspice'
.param vds=1.8 vgs=1.8
.option PARHIER = LOCAL
.option PORT_VOLTAGE_SCALE_TO_2X = 1
.option RUNLVL = 3
.option WDF=1
.temp 25
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09-SP2
*Sat Apr 30 02:24:33 2022
.global gnd!
********************************************************************************
* Library : mos_testing
* Cell : nmos4t_hvt_iv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm0 net1 net4 gnd! gnd! n105_hvt w=0.1u l=0.05u nf=1 m=1
v4 net7 gnd! dc='vgs'
v1 net1 gnd! dc='vds'
r3 net7 net4 r=1k
.dc vgs 0 1.8 .02
.option opfile=1 split_dp=1
.option probe=1
.probe dc v(*) level=1
.probe dc isub(xm0.1)
.end
Complementary MOSFET is a combination of NMOS and PMOS transistor. It is a basic building block of any circuit design. The figure below shows the CMOS circuit and its behaviour depending on the input voltage. Whenever Vin = Vdd, a direct path exixt between Vout and Vss and thus we can say that the capaciors discharges and Vout = 0. However, when Vin = 0, a direct path exist through Vdd and Vout and capacitor charges to Vdd and so also Vout = Vdd.
a) Mos as a switch : We know that, with fiinite ON resistance when |Vgs| > |vt|, curent flows through the circuit and we can say it is turn ON and with infinite OFF resistance whenever Vgs| < |vt|, the circuit is OFF that is there is no current flow from source to drain.
b) Introduction to standard MOS voltage current parameters: The snapshot below shows the CMOS voltage and current parameters. Certain observations are mode based on the parameters
c) Voltage transfer characteristics for static inverter: Certain steps are involved in obtaining the VTC curve of an inverter. The characteristic/ load curve of both NMOS and PMOS transistors are used for the same. Let us assume Vdd =2v and it is long channel device.
Step1: Select few Vgsp value
| VgsP Value | Vin = (VgsP + Vdd) |
|---|---|
| VgsP1 = 0V | Vin1 = 2v |
| VgsP2 = -0.5 | Vin2 = 1.5V |
| VgsP3 = -1 | Vin3 = 1V |
| VgsP4 = -1.5 | Vin4 = 0.5 |
| VgsP5 = -2 | Vin5 = 0V |
Idsp = -Idsn
The curves which was originally in -IdsP and -VdsP for PMOS in 3rd quadrant is now change to 4th quadrant with -VdsP in x axis and Idsn in yaxis and sweep over by Vin = Vgs+Vdd. Now IdsN vs -VdsP curve is drawn for different Vin. The first step of converting VgsP to Vin is completed.
Step 2: Convert VdsP to Vout
Now as we change the VdsP to Vout, everthing remains same except the voltage shifts from -VdsP to Vout eg Vout = 0+2 = 2V i.e the current which is flowing at 2V is “0”iresspective of the value of Vin as the capacitor is fully charge. Now finally the graph shifts to the first quadrant. Also for example Vout = 2-2 = 0. In this we know that the capacitor discharges and a finite amount of Idsn current flows, which can be termed as the charging current. The snapshot of the PMOS load cirve is included below.
Step 3: Load curve for NMOS transistor
| VgsN Value | Vin = VgsN |
|---|---|
| VgsN1 = 0V | Vin1 = 0v |
| VgsN2 = 0.5 | Vin2 = 0.5V |
| VgsN3 = 1 | Vin3 = 1V |
| VgsN4 = 1.5 | Vin4 = 1.5 |
| VgsN5 = 2 | Vin5 = 2V |
Step4: Merge the PMOS and NMOS load curve to obtain the VTC Finally for VTC the curve between Vin and Vout is to be drawn. As, the Vin and Vout of both PMOS and NMOS are same. Thus in order to obtain the curves we need the superimpose the PMOS load curve over the NMOS load curve. This is necessary as the intersection point of both the load curves defines the region of operation of the transistor. For example, when Vin = 0V the point of intersection or Vout is 2V, From the figure we observe that PMOS is in linear region and NMOS is in saturation region and so on. Thus, by this way we can easily determine for the various sweep in voltage of Vin what is Vout and status of both the transistors. The voltage transfer characteristic of CMOS inverter is as shown in the snapshot below.
The following set of programs analyis the static and dynamic characteristics for CMOS inverter of differnt sizes. Here, the CMOS robustness for the variation in switching threshold, noise margin, power supply variation and device variation is plotted and verified as per theoritical understanding. Also, the change in the dynamic characteristic (rise delay, fall delay) is observe and the importance of selecting a proper set of transistor size as per requirement is seen.
- Spice deck to plot the vtc characteristics of a cmos inverter circuit for wp/lp = 2.34wn/ln
Spice deck to plot the vtc characteristics of a cmos inverter circuit for wp/lp = 2.34wn/ln
*Model description
.param temp = 27
*Netlist description
XM1 out in Vdd Vdd sky130_fd_pr__pfet_01v8 W =0.84 L = 0.15
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W =0.36 L = 0.15
cload out 0 50fF
Vdd Vdd 0 1.8V
Vin in 0 1.8V
*include model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*simulation commands
.op
.dc Vin 0 1.8V 0.01
*interactive interpretor command
.control
run
display
setplot dc1
plot in out
.endc
.end
- Spice deck to plot the dynamic characteristics(rise and fall delay) of cmos inverter circuit for wp/lp = 2.34wn/ln
Spice deck to plot the dynamic characteristics(rise and fall delay) of cmos inverter circuit for wp/lp = 2.34wn/ln
*Model descriptio
.param temp = 27
*Netlist description
XM1 out in Vdd Vdd sky130_fd_pr__pfet_01v8 W =0.84 L = 0.15
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W =0.36 L = 0.15
cload out 0 50fF
Vdd Vdd 0 1.8V
Vin in 0 pulse 0 1.8V 0 10ps 10ps 2ns 4ns
*include model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*simulation commands
.op
.tran 10ps 10ns
*interactive interpretor command
.control
run
display
setplot tran1
plot in out
.endc
.end
- Spice deck to plot the dynamic characteristics(rise and fall delay) of cmos inverter circuit for wp/lp = wn/ln
Spice deck to plot the dynamic characteristics(rise and fall delay) of cmos inverter circuit for wp/lp = wn/ln
*Model description
.param temp = 27
*Netlist description
XM1 out in Vdd Vdd sky130_fd_pr__pfet_01v8 W =0.84 L = 0.15
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W =0.84 L = 0.15
cload out 0 50fF
Vdd Vdd 0 1.8V
Vin in 0 pulse 0 1.8V 0 10ps 10ps 2ns 4ns
*include model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*simulation commands
.op
.tran 10ps 10ns
*interactive interpretor command
.control
run
display
setplot tran1
plot in out
.endc
.end
The delay table for different PMOS size with respect to constant NMOS size using sky130 technology file for tt, ss and ff corner is as shown below. The analysis starts from w = 0.42 and l = 0.15um. The programs required for evaluation of the rise delay and fall delay for different (w/l) ratio of NMOS and PMOS transistor is here and so is the static characterisctics switching threshold evaluation. From each of the table it is observe thar for (w/l)p = 2.5(w/l)n, the rise and fall propagation delay is almost equal which makes them perfect for clock network. The other CMOS transistor can be use as regular buffers in other appliactions as in data path. Also seen that with increase in the PMOS size the rise propagation delay start decreasing indicating that the capacitor is charged faster as compared to discharging. The switching threshold volatges are also included for the different transistor sizes.
Ron(PMOS) ~ 2.5Ron(NMOS)*
Table1: Delay table using sky130 tt corner
| wp/lp | x.wn/ln | Rise delay (ps) | Fall delay(ps) | Switching threshold (V) |
|---|---|---|---|---|
| wp/lp | 1(wn/ln) | 149 | 73 | 0.831765 |
| wp/lp | 2(wn/ln) | 88 | 75 | 0.889839 |
| wp/lp | 2.5(wn/ln) | 73 | 75 | 0.895161 |
| wp/lp | 3(wn/ln ) | 69 | 76 | 0.895161 |
| wp/lp | 4(wn/ln) | 59 | 78 | 0.916129 |
| wp/lp | 5(wn/ln) | 52 | 80 | 0.929032 |
Table2: Delay table using sky130 ff corner
| wp/lp | x.wn/ln | Rise delay (ps) | Fall delay(ps) | switching threshold (V) |
|---|---|---|---|---|
| wp/lp | 1(wn/ln) | 114 | 60 | 0.809677 |
| wp/lp | 2(wn/ln) | 69 | 62 | 0.877419 |
| wp/lp | 2.5(wn/ln) | 60 | 62 | 0.887097 |
| wp/lp | 3(wn/ln) | 54 | 62 | 0.891935 |
| wp/lp | 4(wn/ln) | 48 | 64 | 0.914516 |
| wp/lp | 5(wn/ln) | 42 | 65 | 0.935484 |
Table3: Delay table using sky130 ss corner
| wp/lp | x.wn/ln | Rise delay (ps) | Fall delay(ps) | switching threshold (V) |
|---|---|---|---|---|
| wp/lp | 1(wn/ln) | 226 | 93 | 0.85 |
| wp/lp | 2(wn/ln) | 122 | 96 | 0.906452 |
| wp/lp | 2.5(wn/ln) | 103 | 97 | 0.908065 |
| wp/lp | 3(wn/ln) | 95 | 98 | 0.903226 |
| wp/lp | 4(wn/ln) | 76 | 100 | 0.922581 |
| wp/lp | 5(wn/ln) | 64 | 102 | 0.935484 |
- Spice deck to find the noise margin of a cmos inverter circuit for (wp/lp=1/0.15) and (wn/ln=0.36/0.15)
Spice deck to find the noise margin of a cmos inverter circuit for (wp/lp=1/0.15) and (wn/ln=0.36/0.15)
*Model description
.param temp = 27
*Netlist description
XM1 out in Vdd Vdd sky130_fd_pr__pfet_01v8 W =1 L = 0.15
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W =0.36 L = 0.15
cload out 0 50fF
Vdd Vdd 0 1.8V
Vin in 0 1.8V
*include model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*simulation commands
.op
.dc Vin 0 1.8V 0.01
*interactive interpretor commandw
.control
run
display
setplot dc1
plot out vs in
.endc
.end
The noise margin defines the maximum allowable range for which the device can operate properly. NMH and NML is calculated using the formula below:
NMH = VOH - VIH
NML = VIL - VOLFrom the above plot
VOH = 1.63125
VIH = 0.964516
NMH = 1.63125 - 0.964516
= 0.666734VIL = 0.801613
VOL = 0.121875
NML = 0.801613 - 0.121875
= 0.679738- Spice deck to check the dc characteristics of the CMOS transistor with varying power supply
This program shows another CMOS robustness characteristics, power supply variation. The output below shows that the change input voltage of CMOS keeping the size of the transistor constant does not have any impact on the behaviour of CMOS.
Spice deck to check the dc characteristics of the CMOS transistor with varying power supply
*Model parameters
.param temp =27
*Netlist description
XM1 out in Vdd Vdd sky130_fd_pr__pfet_01v8 w=1 l=0.15
XM2 out in 0 0 sky130_fd_pr__nfet_01v8 w=0.36 l=0.15
cload out 0 50fF
Vin in 0 1.8V
Vdd Vdd 0 1.8V
*include model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*Control command
.control
let powersupply = 1.8
alter Vdd = powersupply
let supplyvoltagevariation = 0
dowhile supplyvoltagevariation < 6
dc Vin 0 1.8 0.01
let powersupply = powersupply - 0.2
alter Vdd = powersupply
let supplyvoltagevariation = supplyvoltagevariation + 1
end
plot dc1.out vs in dc2.out vs in dc3.out vs in dc4.out vs in dc5.out vs in xlabel "input voltage [V]"
ylabel "output voltage [V]" title "Inverter dc characteristics as a function of supply voltage"
.endc
.end
- Spice deck to plot the dc characteristics of a cmos inverter circuit for 7wp/0.15lp and 0.42wn/0.15ln
This program shows another robust behaviour of the CMOS inverter, device variation. As seen from the output characteristics it is observe that the no change in the behavioural aspect of CMOS occurs accept that the switching threshold is shifted towards right.
Spice deck to plot the dc characteristics of a cmos inverter circuit for 7wp/0.15lp and 0.42wn/0.15ln
*Model Description
.param temp=27
*Including model file
.lib "../sky130_fd_pr/models/sky130.lib.spice" tt
*Netlist Description
XM1 out in vdd vdd sky130_fd_pr__pfet_01v8 w=7 l=0.15
XM2 out in 0 0 sky130_fd_pr__nfet_01v8 w=0.42 l=0.15
Cload out 0 50fF
Vdd vdd 0 1.8V
Vin in 0 1.8V
*simulation commands
.op
.dc Vin 0 1.8 0.01
*interactive interpretor command
.control
run
setplot dc1
display
plot out vs in
.endc
.end
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
- Vrushab Damle