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simplify address decoder #11

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bieganski opened this issue Feb 27, 2022 · 0 comments

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bieganski commented Feb 27, 2022 •

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What happens?

Currently address decoder allows for whole 32-bit space to be used, which is a killer for FPGA resources.
Relevant code:

with m.If((req_addr >= start_addr) & (req_addr <= max_legal_addr)):
    m.d.comb += [
            slv_bus.connect(self.bus, exclude=["adr"]),
            slv_bus.adr.eq(req_addr - start_addr),
            matches[i].eq(1),
        ]

32-bit comparators are used.
Instead we should force some address space restrictions on periph. devices registration and simplify decoder's logic.

bieganski mentioned this issue

interconnect to be unified #12

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