virtual memory: trap on invalid access

[bieganski]

What happens?

Virtual memory system in mtkCPU is well-tested, but only for proper memory configuration.
For error conditions only error register is written (no trap occurs at all):

self.error_code = Signal(Issue)
        def error(code: Issue):
            m.d.sync += self.error_code.eq(code)

content of error function should update PC with mtvec and change main FSM state to FETCH.