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Commit 1632db8

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fixup! renesas_ra: Confirm flash writes/erases
1 parent 0c3a93a commit 1632db8

1 file changed

Lines changed: 18 additions & 15 deletions

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‎src/target/renesas_ra.c‎

Lines changed: 18 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,9 +1138,8 @@ static bool renesas_mf3_pe_mode(target_s *const target, const pe_mode_e pe_mode)
11381138
platform_timeout_s timeout;
11391139
platform_timeout_set(&timeout, 10);
11401140

1141-
/* Wait for the operation to complete or timeout, Read until FENTRYR and FRDY is set */
1142-
while (target_mem32_read16(target, MF3_FENTRYR) != fentryr ||
1143-
!(target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY)) {
1141+
/* Wait for the operation to complete or timeout, Read until FENTRYR is set */
1142+
while (target_mem32_read16(target, MF3_FENTRYR) != fentryr) {
11441143
if (target_check_error(target) || platform_timeout_is_expired(&timeout))
11451144
return false;
11461145
}
@@ -1155,6 +1154,7 @@ static bool renesas_mf3_error_check(target_s *const target, const uint16_t error
11551154

11561155
/* Check if status indicates a programming error */
11571156
if (fstatr2 & error_bits) {
1157+
DEBUG_WARN("Flash encountered an error; FSTATR2: 0x%x\n", fstatr2);
11581158
/* Stop the flash */
11591159
target_mem32_write8(target, MF3_FCR, MF3_FCR_STOP);
11601160

@@ -1171,6 +1171,8 @@ static bool renesas_mf3_error_check(target_s *const target, const uint16_t error
11711171
/* Reset the flash controller */
11721172
target_mem32_write8(target, MF3_FRESETR, MF3_FRESETR_RESET);
11731173
target_mem32_write8(target, MF3_FRESETR, 0);
1174+
1175+
return true;
11741176
}
11751177

11761178
return false;
@@ -1180,13 +1182,11 @@ static bool renesas_mf3_prepare(target_flash_s *const flash)
11801182
{
11811183
target_s *const target = flash->t;
11821184

1183-
if (!(target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY) ||
1184-
target_mem32_read16(target, MF3_FENTRYR) != 0) {
1185-
DEBUG_ERROR("Flash is not ready, may be hanging mid unfinished command due to something going wrong, "
1186-
"please power on reset the device\n");
1187-
1188-
return false;
1189-
}
1185+
/* This doesn't check to see if the FRDY bit is set, unlike the RV40 flash,
1186+
* as FRDY is only set after a command executes and is zero on reset. Thus,
1187+
* if you've attached after a reset and haven't done anything, it will be
1188+
* zero and erroneously trigger the check.
1189+
*/
11901190

11911191
/* Code flash or data flash operation */
11921192
const bool code_flash = flash->start < RENESAS_CF_END;
@@ -1255,8 +1255,8 @@ static bool renesas_mf3_flash_erase(target_flash_s *const flash, target_addr_t a
12551255

12561256
platform_timeout_set(&timeout, 10);
12571257

1258-
/* Read FRDY bit until it has been set to 1 indicating that the current operation is complete.*/
1259-
while (!(target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY)) {
1258+
/* Read FRDY bit until it has been set to 0. */
1259+
while ((target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY)) {
12601260
if (target_check_error(target) || platform_timeout_is_expired(&timeout))
12611261
return false;
12621262
}
@@ -1319,14 +1319,17 @@ static bool renesas_mf3_flash_write(target_flash_s *const flash, target_addr_t d
13191319

13201320
platform_timeout_set(&timeout, 10);
13211321

1322-
/* Read FRDY bit until it has been set to 1 indicating that the current operation is complete.*/
1323-
while (!(target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY)) {
1322+
/* Read FRDY bit until it has been set to 0 */
1323+
while ((target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY)) {
13241324
if (target_check_error(target) || platform_timeout_is_expired(&timeout))
13251325
return false;
13261326
}
1327+
1328+
if (renesas_mf3_error_check(target, MF3_FSTATR2_PRGERR | MF3_FSTATR2_ILGLERR))
1329+
return false;
13271330
}
13281331

1329-
return !renesas_mf3_error_check(target, MF3_FSTATR2_PRGERR | MF3_FSTATR2_ILGLERR);
1332+
return true;
13301333
}
13311334

13321335
/* Reads the 16-byte unique id */

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