!experimental! rvswd: working implementation (change dump)

Author: perigoso

src/include/platform_support.h

@@ -50,6 +50,9 @@ void platform_timeout_set(platform_timeout_s *target, uint32_t ms);
 bool platform_timeout_is_expired(const platform_timeout_s *target);
 void platform_delay(uint32_t ms);
 
+void platform_critical_enter(void);
+void platform_critical_exit(void);
+
 #define POWER_CONFLICT_THRESHOLD 5U /* in 0.1V, so 5 stands for 0.5V */
 
 extern bool connect_assert_nrst;

src/platforms/common/rvswd.c

@@ -46,16 +46,20 @@
 /**
  * RVSWD I/O is shared with SWD
  */
-#define RVSWD_DIO_DIR_PORT SWDIO_DIR_PORT
-#define RVSWD_DIO_PORT     SWDIO_PORT
-#define RVSWD_CLK_PORT     SWCLK_PORT
-#define RVSWD_DIO_DIR_PIN  SWDIO_DIR_PIN
-#define RVSWD_DIO_PIN      SWDIO_PIN
-#define RVSWD_CLK_PIN      SWCLK_PIN
+#define RVSWD_DIO_PORT SWDIO_PORT
+#define RVSWD_DIO_PIN  SWDIO_PIN
+
+#define RVSWD_CLK_PORT SWCLK_PORT
+#define RVSWD_CLK_PIN  SWCLK_PIN
 
 #define RVSWD_DIO_MODE_FLOAT SWDIO_MODE_FLOAT
 #define RVSWD_DIO_MODE_DRIVE SWDIO_MODE_DRIVE
 
+typedef enum rvswd_direction_t {
+	RVSWD_DIRECTION_INPUT,
+	RVSWD_DIRECTION_OUTPUT
+} rvswd_direction_t;
+
 rvswd_proc_s rvswd_proc;
 
 static void rvswd_start(void) __attribute__((optimize(3)));
@@ -84,19 +88,21 @@ void rvswd_init(void)
 	rvswd_proc.seq_out = rvswd_seq_out;
 }
 
-static void rvswd_set_dio_direction(bool output)
+static void rvswd_set_dio_direction(rvswd_direction_t direction)
 {
 	/* Do nothing if the direction is already set */
-	static bool current_direction = false;
-	if (output == current_direction)
+	/* FIXME: this internal state may become invalid if the IO is modified elsewhere (e.g. SWD) */
+	static rvswd_direction_t current_direction = RVSWD_DIRECTION_INPUT;
+	if (direction == current_direction)
 		return;
 
 	/* Change the direction */
-	if (output)
+	if (direction == RVSWD_DIRECTION_OUTPUT) {
 		RVSWD_DIO_MODE_DRIVE();
-	else
+	} else {
 		RVSWD_DIO_MODE_FLOAT();
-	current_direction = output;
+	}
+	current_direction = direction;
 }
 
 static void rvswd_start(void)
@@ -106,9 +112,9 @@ static void rvswd_start(void)
 	 */
 
 	/* Setup for the start sequence by setting the bus to the idle state */
-	rvswd_set_dio_direction(true);
+	rvswd_set_dio_direction(RVSWD_DIRECTION_OUTPUT);
+	gpio_set(RVSWD_DIO_PORT, RVSWD_DIO_PIN);
 	gpio_set(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
-	gpio_set(RVSWD_DIO_DIR_PORT, RVSWD_DIO_PIN);
 
 	/* Ensure the bus is idle for a period */
 	rvswd_hold_period();
@@ -124,14 +130,9 @@ static void rvswd_stop(void)
 	 * DIO rising edge while CLK is idle high marks a STOP condition
 	 */
 
-	/*
-	 * Setup for the stop condition by driving the CLK and DIO low
-	 *
-	 * It is likely that the previous sequence left the CLK low already
-	 * but a redundant low CLK set ensures we don't issue a start condition by mistake
-	 */
+	/* Setup for the stop condition by driving the CLK and DIO low */
 	gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
-	rvswd_set_dio_direction(true);
+	rvswd_set_dio_direction(RVSWD_DIRECTION_OUTPUT);
 	gpio_clear(RVSWD_DIO_PORT, RVSWD_DIO_PIN);
 
 	/* Ensure setup for a period */
@@ -153,14 +154,16 @@ static uint32_t rvswd_seq_in_clk_delay(const size_t clock_cycles)
 		gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
 		rvswd_hold_period();
 
-		/* Sample the DIO line and raise the CLK, then hold for a period */
+		/* Sample the DIO line and Raise the CLK, then hold for a period */
 		value |= gpio_get(RVSWD_DIO_PORT, RVSWD_DIO_PIN) ? (1U << (cycle - 1U)) : 0U;
 		gpio_set(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
 		rvswd_hold_period();
 	}
 
-	/* Leave the CLK low and return the value */
-	gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+	// /* Leave the CLK low and return the value */
+	// gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+
+	/* Leave the CLK high and return the value */
 	return value;
 }
 
@@ -176,19 +179,19 @@ static uint32_t rvswd_seq_in_no_delay(const size_t clock_cycles)
 		/* Sample the DIO line and raise the CLK */
 		value |= gpio_get(RVSWD_DIO_PORT, RVSWD_DIO_PIN) ? (1U << (cycle - 1U)) : 0U;
 		gpio_set(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
-
-		__asm__("nop"); /* Ensure there's time for the CLK to settle */
 	}
 
-	/* Leave the CLK low and return the value */
-	gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+	// /* Leave the CLK low and return the value */
+	// gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+
+	/* Leave the CLK high and return the value */
 	return value;
 }
 
 static uint32_t rvswd_seq_in(size_t clock_cycles)
 {
 	/* Set the DIO line to float to give control to the target */
-	rvswd_set_dio_direction(false);
+	rvswd_set_dio_direction(RVSWD_DIRECTION_INPUT);
 
 	/* Delegate to the appropriate sequence in routine depending on the clock divider */
 	if (target_clk_divider != UINT32_MAX)
@@ -211,8 +214,10 @@ static void rvswd_seq_out_clk_delay(const uint32_t dio_states, const size_t cloc
 		rvswd_hold_period();
 	}
 
-	/* Leave the CLK low */
-	gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+	// /* Leave the CLK low */
+	// gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+
+	/* Leave the CLK high and return */
 }
 
 static void rvswd_seq_out_no_delay(const uint32_t dio_states, const size_t clock_cycles)
@@ -227,14 +232,16 @@ static void rvswd_seq_out_no_delay(const uint32_t dio_states, const size_t clock
 		gpio_set(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
 	}
 
-	/* Leave the CLK low */
-	gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+	// /* Leave the CLK low */
+	// gpio_clear(RVSWD_CLK_PORT, RVSWD_CLK_PIN);
+
+	/* Leave the CLK high and return */
 }
 
 static void rvswd_seq_out(const uint32_t dio_states, const size_t clock_cycles)
 {
 	/* Set the DIO line to drive to give us control */
-	rvswd_set_dio_direction(true);
+	rvswd_set_dio_direction(RVSWD_DIRECTION_OUTPUT);
 
 	/* Delegate to the appropriate sequence in routine depending on the clock divider */
 	if (target_clk_divider != UINT32_MAX)

src/platforms/common/stm32/critical.c

@@ -0,0 +1,62 @@
+/*
+ * This file is part of the Black Magic Debug project.
+ *
+ * Copyright (C) 2025 1BitSquared <info@1bitsquared.com>
+ * Written by Rafael Silva <perigoso@riseup.net>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file implements the RVSWD interface
+ *
+ * It's mostly the same routines as the SWD interface, with some RVSWD specifics
+ */
+
+#include "general.h"
+#include "platform.h"
+
+#include <libopencm3/cm3/cortex.h>
+
+static uint32_t nested_critical = 0;
+static uint32_t primask = 0;
+
+void platform_critical_enter(void)
+{
+	if (nested_critical == 0) {
+		primask = cm_mask_interrupts(1U);
+	}
+	nested_critical++;
+}
+
+void platform_critical_exit(void)
+{
+	nested_critical--;
+	if (nested_critical == 0) {
+		cm_mask_interrupts(primask);
+	}
+}

src/platforms/common/stm32/meson.build

@@ -31,6 +31,7 @@
 platform_stm32_includes = include_directories('.')
 
 platform_stm32_sources = files(
+	'critical.c',
 	'serialno.c',
 	'timing_stm32.c',
 )

src/platforms/hosted/platform.c

@@ -198,6 +198,16 @@ void platform_init(int argc, char **argv)
 	}
 }
 
+void platform_critical_enter(void)
+{
+	/* Nothing to do */
+}
+
+void platform_critical_exit(void)
+{
+	/* Nothing to do */
+}
+
 bool bmda_swd_scan(const uint32_t targetid)
 {
 	bmda_probe_info.is_jtag = false;

src/platforms/hosted/wchlink_riscv_dtm.c

@@ -58,10 +58,13 @@ static void wchlink_riscv_dtm_init(riscv_dmi_s *const dmi)
 	/* WCH-Link doesn't have any mechanism to identify the DTM manufacturer, so we'll just assume it's WCH */
 	dmi->designer_code = NOT_JEP106_MANUFACTURER_WCH;
 
-	dmi->version = RISCV_DEBUG_0_13; /* Assumption, unverified */
+	dmi->version = RISCV_DEBUG_UNSPECIFIED; /* Not available */
 
-	/* WCH-Link has a fixed address width of 8 bits, limited by the USB protocol (is RVSWD also fixed?) */
-	dmi->address_width = 8U;
+	/*
+	 * WCH-Link has a fixed address width of 7 bits,
+	 * technically limited by the USB protocol to 8 bits but the underlying protocols are 7 bits
+	 */
+	dmi->address_width = 7U;
 
 	dmi->read = wchlink_riscv_dmi_read;
 	dmi->write = wchlink_riscv_dmi_write;
@@ -72,19 +75,19 @@ static void wchlink_riscv_dtm_init(riscv_dmi_s *const dmi)
 static bool wchlink_riscv_dmi_read(riscv_dmi_s *const dmi, const uint32_t address, uint32_t *const value)
 {
 	uint8_t status = 0;
-	const bool result = wchlink_transfer_dmi(RV_DMI_READ, address, 0, value, &status);
+	const bool result = wchlink_transfer_dmi(RV_DMI_OP_READ, address, 0, value, &status);
 
 	/* Translate error 1 into RV_DMI_FAILURE per the spec, also write RV_DMI_FAILURE if the transfer failed */
-	dmi->fault = !result || status == 1U ? RV_DMI_FAILURE : status;
+	dmi->fault = !result || status == RV_DMI_RESERVED ? RV_DMI_FAILURE : status;
 	return dmi->fault == RV_DMI_SUCCESS;
 }
 
 static bool wchlink_riscv_dmi_write(riscv_dmi_s *const dmi, const uint32_t address, const uint32_t value)
 {
 	uint8_t status = 0;
-	const bool result = wchlink_transfer_dmi(RV_DMI_WRITE, address, value, NULL, &status);
+	const bool result = wchlink_transfer_dmi(RV_DMI_OP_WRITE, address, value, NULL, &status);
 
 	/* Translate error 1 into RV_DMI_FAILURE per the spec, also write RV_DMI_FAILURE if the transfer failed */
-	dmi->fault = !result || status == 1U ? RV_DMI_FAILURE : status;
+	dmi->fault = !result || status == RV_DMI_RESERVED ? RV_DMI_FAILURE : status;
 	return dmi->fault == RV_DMI_SUCCESS;
 }

src/target/riscv32.c

@@ -240,7 +240,7 @@ static void riscv32_abstract_mem_read(
 	const uint32_t command = RV_DM_ABST_CMD_ACCESS_MEM | RV_ABST_READ | (access_width << RV_ABST_MEM_ACCESS_SHIFT) |
 		(access_length < len ? RV_ABST_MEM_ADDR_POST_INC : 0U);
 	/* Write the address to read to arg1 */
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA1, src))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(1U), src))
 		return;
 	uint8_t *const data = (uint8_t *)dest;
 	for (size_t offset = 0; offset < len; offset += access_length) {
@@ -249,7 +249,7 @@ static void riscv32_abstract_mem_read(
 			return;
 		/* Extract back the data from arg0 */
 		uint32_t value = 0;
-		if (!riscv_dm_read(hart->dbg_module, RV_DM_DATA0, &value))
+		if (!riscv_dm_read(hart->dbg_module, RV_DM_DATA(0U), &value))
 			return;
 		riscv32_unpack_data(data + offset, value, access_width);
 	}
@@ -265,13 +265,13 @@ static void riscv32_abstract_mem_write(
 	const uint32_t command = RV_DM_ABST_CMD_ACCESS_MEM | RV_ABST_WRITE | (access_width << RV_ABST_MEM_ACCESS_SHIFT) |
 		(access_length < len ? RV_ABST_MEM_ADDR_POST_INC : 0U);
 	/* Write the address to write to arg1 */
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA1, dest))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(1U), dest))
 		return;
 	const uint8_t *const data = (const uint8_t *)src;
 	for (size_t offset = 0; offset < len; offset += access_length) {
 		/* Pack the data to write into arg0 */
 		uint32_t value = riscv32_pack_data(data + offset, access_width);
-		if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA0, value))
+		if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(0U), value))
 			return;
 		/* Execute the write */
 		if (!riscv_dm_write(hart->dbg_module, RV_DM_ABST_COMMAND, command) || !riscv_command_wait_complete(hart))
@@ -604,23 +604,23 @@ static void riscv32_abstract_progbuf_mem_read(
 	 * c.lw x8,0(x11) // Pull the address from DATA1
 	 * c.lw x9,0(x8)  // Read the data at that location
 	 */
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF0, 0x40044180U))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF(0U), 0x40044180U))
 		return;
 
 	/* 
 	 * progbuf 1
 	 * c.nop		  // alternately, `c.addi x8, 4` , for auto-increment (0xc1040411)
 	 * c.sw x9, 0(x10) // Write back to DATA0
 	 */
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF1, 0xc1040001U))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF(1U), 0xc1040001U))
 		return;
 
 	/* 
 	 * progbuf 2
 	 * c.sw x8, 0(x11) // Write addy to DATA1
 	 * c.ebreak
 	 */
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF2, 0x9002c180U))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF(2U), 0x9002c180U))
 		return;
 
 	/* StaticUpdatePROGBUFRegs */
@@ -631,11 +631,11 @@ static void riscv32_abstract_progbuf_mem_read(
 	}
 	DEBUG_INFO("rr: %08" PRIx32 "\n", rr);
 	const uint32_t data0_offset = 0xe0000000U | (rr & 0x7ffU);
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA0, data0_offset)) // DATA0's location in memory.
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(0U), data0_offset)) // DATA0's location in memory.
 		return;
 	if (!riscv_dm_write(hart->dbg_module, RV_DM_ABST_COMMAND, 0x0023100aU)) // Copy data to x10
 		return;
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA0, data0_offset + 4U)) // DATA1's location in memory.
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(0U), data0_offset + 4U)) // DATA1's location in memory.
 		return;
 	if (!riscv_dm_write(hart->dbg_module, RV_DM_ABST_COMMAND, 0x0023100bU)) // Copy data to x11
 		return;
@@ -654,14 +654,14 @@ static void riscv32_abstract_progbuf_mem_read(
 	// if (!riscv_dm_write(hart->dbg_module, RV_DM_ABST_AUTO, 1U))
 	// 	return;
 
-	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA1, src))
+	if (!riscv_dm_write(hart->dbg_module, RV_DM_DATA(1U), src))
 		return;
 	if (!riscv_dm_write(hart->dbg_module, RV_DM_ABST_COMMAND, 0x00241000U) || !riscv_command_wait_complete(hart))
 		return;
 
 	/* Extract back the data from arg0 */
 	uint32_t value = 0;
-	if (!riscv_dm_read(hart->dbg_module, RV_DM_DATA0, &value))
+	if (!riscv_dm_read(hart->dbg_module, RV_DM_DATA(0U), &value))
 		return;
 
 	riscv32_unpack_data(dest, value, access_width);