diff --git a/.gitignore b/.gitignore index 4c9e245..1422057 100644 --- a/.gitignore +++ b/.gitignore @@ -1,23 +1,2 @@ -dist -dist-* -cabal-dev -*.o *.hi -*.hie -*.chi -*.chs.h -*.dyn_o -*.dyn_hi -.hpc -.hsenv -.cabal-sandbox/ -cabal.sandbox.config -*.prof -*.aux -*.hp -*.eventlog -.stack-work/ -cabal.project.local -cabal.project.local~ -.HTF/ -.ghc.environment.* +*.o diff --git a/.gitmodules b/.gitmodules index 877ef83..d06d9bf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ -[submodule "work/blarney"] - path = work/blarney - url = https://github.com/mn416/blarney +[submodule "blarney"] + path = blarney + url = https://github.com/JonasAlaif/blarney.git + branch = jf613-change-test-script diff --git a/Documentation/README.md b/Documentation/README.md new file mode 100644 index 0000000..89171ac --- /dev/null +++ b/Documentation/README.md @@ -0,0 +1 @@ +A read-only copy of the source latex can be found at https://www.overleaf.com/project/5e30193d717c320001b14145 diff --git a/diss/diss_backups/jf613_final.pdf b/Documentation/blarneycheck:_Property-based_Testing_for_Hardware.pdf similarity index 100% rename from diss/diss_backups/jf613_final.pdf rename to Documentation/blarneycheck:_Property-based_Testing_for_Hardware.pdf diff --git a/work/BuggySuite/ActoraStack.hs b/Examples/ActoraStack/ActoraStack.hs similarity index 97% rename from work/BuggySuite/ActoraStack.hs rename to Examples/ActoraStack/ActoraStack.hs index 7c6246b..4914110 100644 --- a/work/BuggySuite/ActoraStack.hs +++ b/Examples/ActoraStack/ActoraStack.hs @@ -68,8 +68,8 @@ makeStackSpec = do testBench :: Module () testBench = do - stkGolden :: Stack 3 (Bit 2) <- makeStackSpec - stkActora :: Stack 3 (Bit 2) <- makeStack + stkGolden :: Stack 3 (Bit 1) <- makeStackSpec + stkActora :: Stack 3 (Bit 1) <- makeStack -- Note 3: Cannot copy top two elements from stack maxSize :: Reg (Bit 3) <- makeReg 0 topTwo :: Reg (Bit 2) <- makeReg 0 @@ -145,4 +145,4 @@ testBench = do -- =============== main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "ActoraStack-Verilog/" diff --git a/Examples/ActoraStack/ActoraStack.out b/Examples/ActoraStack/ActoraStack.out new file mode 100644 index 0000000..8785d21 --- /dev/null +++ b/Examples/ActoraStack/ActoraStack.out @@ -0,0 +1,3 @@ +- All tests passed to depth 0 at time 0 - +- All tests passed to depth 1 at time 76 - +=== All tests passed to maximum specified depth of 2 at time 4408 === diff --git a/work/BuggySuite/ActoraStack_Impl.hs b/Examples/ActoraStack/ActoraStack_Impl.hs similarity index 100% rename from work/BuggySuite/ActoraStack_Impl.hs rename to Examples/ActoraStack/ActoraStack_Impl.hs diff --git a/Examples/ActoraStack/Makefile b/Examples/ActoraStack/Makefile new file mode 100644 index 0000000..ef3a44f --- /dev/null +++ b/Examples/ActoraStack/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) ActoraStack.hs + +clean: + rm -rf *.o *.hi ActoraStack ActoraStack-Verilog diff --git a/work/BuggySuite/BRAMStack.hs b/Examples/BRAMStack/BRAMStack.hs similarity index 95% rename from work/BuggySuite/BRAMStack.hs rename to Examples/BRAMStack/BRAMStack.hs index 32c1dde..bfd66e3 100644 --- a/work/BuggySuite/BRAMStack.hs +++ b/Examples/BRAMStack/BRAMStack.hs @@ -88,8 +88,8 @@ makeStackSpec logSize = -- Top-level module testBench :: Module () testBench = do - stkGolden :: Stack (Bit 5) <- makeStackSpec 5 - stkBRAM :: Stack (Bit 5) <- makeBRAMStack 5 + stkGolden :: Stack (Bit 2) <- makeStackSpec 5 + stkBRAM :: Stack (Bit 2) <- makeBRAMStack 5 let topEq = stkGolden.top .==. stkBRAM.top let prop_TopEq = Assert' (stkGolden.isEmpty .|. topEq) (display_ (stkGolden.top) " v " (stkBRAM.top)) @@ -115,4 +115,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "BRAMStack-Verilog/" diff --git a/Examples/BRAMStack/BRAMStack.out b/Examples/BRAMStack/BRAMStack.out new file mode 100644 index 0000000..6b5cab8 --- /dev/null +++ b/Examples/BRAMStack/BRAMStack.out @@ -0,0 +1,12 @@ +- All tests passed to depth 0 at time 0 - +- All tests passed to depth 1 at time 10 - +- All tests passed to depth 2 at time 85 - +- All tests passed to depth 3 at time 585 - +- All tests passed to depth 4 at time 3710 - +=== Found failing case at depth 5 after 21722 ticks: TopEq {1 v 0} === +0: Push 0x1 +1: Push 0x0 +2: Push 0x0 +3: Pop +4: Pop +5: 'TopEq {1 v 0}' fails diff --git a/Examples/BRAMStack/Makefile b/Examples/BRAMStack/Makefile new file mode 100644 index 0000000..188d440 --- /dev/null +++ b/Examples/BRAMStack/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) BRAMStack.hs + +clean: + rm -rf *.o *.hi BRAMStack BRAMStack-Verilog diff --git a/work/BuggySuite/CPU.hs b/Examples/CPU/CPU.hs similarity index 85% rename from work/BuggySuite/CPU.hs rename to Examples/CPU/CPU.hs index 14f5a6f..e828c12 100644 --- a/work/BuggySuite/CPU.hs +++ b/Examples/CPU/CPU.hs @@ -44,16 +44,21 @@ testBench = do ] let prop_hazard = Forall \(StoreInstr si1 :: StoreInstr) -> Forall \(branchOffset :: Bit 4) -> - Forall \(StoreInstr si2 :: StoreInstr) -> Forall \(two :: Bit 1) -> WhenRecipe true do + -- Forall \(StoreInstr si2 :: StoreInstr) -- Takes too long to simulate + Forall \(si2rD :: RegId) + -> Forall \(two :: Bit 1) -> WhenRecipe true do Seq [ Action do (instr <== si1) , Action do (instr <== 0b10 # branchOffset # si1.rD) -- si1.rD => Data hazard - , If two (Action (instr <== nop)) (Action noAction) -- Delay next instruction by either 0 or 1 clocks - , Action do (instr <== si2) -- Branched? => Control hazard 1 or 2 cycles after branch + , If two (Action (instr <== nop)) Skip -- Delay next instruction by either 0 or 1 clocks + -- , Action do (instr <== si2) -- Branched? => Control hazard 1 or 2 cycles after branch + , Action do (instr <== 0b00 # si2rD # (0b1111 :: Bit 4)) , Action do when (si1.imm .==. 0) do -- If didn't branch si2 must have an effect - correctVal <== si2.imm.zeroExtend - correctDest <== si2.rD + -- correctVal <== si2.imm.zeroExtend + -- correctDest <== si2.rD + correctVal <== 0b1111 + correctDest <== si2rD -- Took (4 + two) cycles to execute, however flush sets pc back by 3 cycles, also subtract jump correctPc <== correctPc.val + two.zeroExtend + (si1.imm .==. 0 ? (4, 1 - branchOffset.zeroExtend)) ] @@ -93,4 +98,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" +main = writeVerilogTop testBench "top" "CPU-Verilog/" diff --git a/Examples/CPU/CPU.out b/Examples/CPU/CPU.out new file mode 100644 index 0000000..0dd24da --- /dev/null +++ b/Examples/CPU/CPU.out @@ -0,0 +1,2 @@ +- All tests passed to depth 0 at time 0 - +=== All tests passed to maximum specified depth of 1 at time 127168 === diff --git a/work/BuggySuite/CPU_Impl.hs b/Examples/CPU/CPU_Impl.hs similarity index 100% rename from work/BuggySuite/CPU_Impl.hs rename to Examples/CPU/CPU_Impl.hs diff --git a/Examples/CPU/Makefile b/Examples/CPU/Makefile new file mode 100644 index 0000000..474c8b0 --- /dev/null +++ b/Examples/CPU/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) CPU.hs + +clean: + rm -rf *.o *.hi CPU CPU-Verilog diff --git a/work/BuggySuite/FirstHot.hs b/Examples/FirstHot/FirstHot.hs similarity index 74% rename from work/BuggySuite/FirstHot.hs rename to Examples/FirstHot/FirstHot.hs index 3078124..529db0a 100644 --- a/work/BuggySuite/FirstHot.hs +++ b/Examples/FirstHot/FirstHot.hs @@ -11,9 +11,9 @@ countOnes b = b.toBitList.(map zeroExtend).sumList testBench :: Module () testBench = do - let prop_OneIsHot = Forall \(x :: Bit 30) -> Assert ((x .==. 0 ? (0, 1)) .==. countOnes (firstHot x)) - let prop_HotBitCommon = Forall \(x :: Bit 30) -> Assert (x .&. (firstHot x) .==. (firstHot x)) - let prop_HotBitFirst = Forall \(x :: Bit 30) -> Assert (x .&. ((firstHot x) - 1) .==. 0) + let prop_OneIsHot = Forall \(x :: Bit 25) -> Assert ((x .==. 0 ? (0, 1)) .==. countOnes (firstHot x)) + let prop_HotBitCommon = Forall \(x :: Bit 25) -> Assert (x .&. (firstHot x) .==. (firstHot x)) + let prop_HotBitFirst = Forall \(x :: Bit 25) -> Assert (x .&. ((firstHot x) - 1) .==. 0) let properties = [ ("OneIsHot", prop_OneIsHot) @@ -28,4 +28,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "FirstHot-Verilog/" diff --git a/Examples/FirstHot/FirstHot.out b/Examples/FirstHot/FirstHot.out new file mode 100644 index 0000000..d854052 --- /dev/null +++ b/Examples/FirstHot/FirstHot.out @@ -0,0 +1 @@ +--All tests passed at time 33554431-- diff --git a/Examples/FirstHot/Makefile b/Examples/FirstHot/Makefile new file mode 100644 index 0000000..5ec9f2f --- /dev/null +++ b/Examples/FirstHot/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) FirstHot.hs + +clean: + rm -rf *.o *.hi FirstHot FirstHot-Verilog diff --git a/Examples/Makefile b/Examples/Makefile new file mode 100644 index 0000000..60fdbe8 --- /dev/null +++ b/Examples/Makefile @@ -0,0 +1,15 @@ +top: + +.PHONY: clean +clean: + make -C ActoraStack clean + make -C BRAMStack clean + make -C CPU clean + make -C FirstHot clean + make -C MemAddr clean + make -C RandomCheck clean + make -C Sorter clean + make -C Sums clean + make -C Sums_Parallel clean + make -C Synthesizable clean + diff --git a/Examples/MemAddr/Makefile b/Examples/MemAddr/Makefile new file mode 100644 index 0000000..d2ff893 --- /dev/null +++ b/Examples/MemAddr/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) MemAddr.hs + +clean: + rm -rf *.o *.hi MemAddr MemAddr-Verilog diff --git a/work/BuggySuite/MemAddr.hs b/Examples/MemAddr/MemAddr.hs similarity index 83% rename from work/BuggySuite/MemAddr.hs rename to Examples/MemAddr/MemAddr.hs index c9c8945..3a429d2 100644 --- a/work/BuggySuite/MemAddr.hs +++ b/Examples/MemAddr/MemAddr.hs @@ -1,7 +1,7 @@ import Blarney import BlarneyCheck -newtype MemAddr = MemAddr (Bit 21) deriving (Generic, Bits) +newtype MemAddr = MemAddr (Bit 32) deriving (Generic, Bits) instance Generator MemAddr where -- Initial value is 0x0...0FFF @@ -11,7 +11,7 @@ instance Generator MemAddr where -- Done when all bits are ones isFinal current = pack current .==. ones -- Number of possible values = 2^(41-12) - range = 2^29 + range = 2^20 testBench :: Module () testBench = do @@ -25,4 +25,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" +main = writeVerilogTop testBench "top" "MemAddr-Verilog/" diff --git a/Examples/MemAddr/MemAddr.out b/Examples/MemAddr/MemAddr.out new file mode 100644 index 0000000..410c470 --- /dev/null +++ b/Examples/MemAddr/MemAddr.out @@ -0,0 +1 @@ +--All tests passed at time 1048575-- diff --git a/Examples/RandomCheck/Makefile b/Examples/RandomCheck/Makefile new file mode 100644 index 0000000..cb4808d --- /dev/null +++ b/Examples/RandomCheck/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) RandomCheck.hs + +clean: + rm -rf *.o *.hi RandomCheck RandomCheck-Verilog diff --git a/work/BuggySuite/RandomCheck.hs b/Examples/RandomCheck/RandomCheck.hs similarity index 96% rename from work/BuggySuite/RandomCheck.hs rename to Examples/RandomCheck/RandomCheck.hs index 7293de7..de192d2 100644 --- a/work/BuggySuite/RandomCheck.hs +++ b/Examples/RandomCheck/RandomCheck.hs @@ -43,4 +43,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "RandomCheck-Verilog/" diff --git a/Examples/RandomCheck/RandomCheck.out b/Examples/RandomCheck/RandomCheck.out new file mode 100644 index 0000000..0f69db6 --- /dev/null +++ b/Examples/RandomCheck/RandomCheck.out @@ -0,0 +1,8 @@ +- All tests passed to depth 0 at time 0 - +Custom Random Values: +00, 01, c6, 5f, 1c, 8d, 82, 0b, 78, 59, 7e, f7, 14, 65, ba, 23, f0, b1, 36, 8f, 0c, 3d, f2, 3b, 68, 09, ee, 27, 04, 15, 2a, 53, e0, 61, a6, bf, fc, ed, 62, 6b, 58, b9, 5e, 57, f4, c5, 9a, 83, d0, 11, 16, ef, ec, 9d, d2, 9b, 48, 69, ce, 87, e4, 75, 0a, b3, c0, c1, 86, 1f, dc, 4d, 42, cb, 38, 19, 3e, b7, d4, 25, 7a, e3, b0, 71, f6, 4f, cc, fd, b2, fb, 28, c9, ae, e7, c4, d5, ea, 13, a0, 21, 66, 7f, bc, ad, 22, 2b, 18, 79, 1e, 17, b4, 85, 5a, 43, 90, d1, d6, af, ac, 5d, 92, 5b, 08, 29, 8e, 47, a4, 35, ca, 73, 80, 81, 46, df, 9c, 0d, 02, 8b, f8, d9, fe, 77, 94, e5, 3a, a3, 70, 31, b6, 0f, 8c, bd, 72, bb, e8, 89, 6e, a7, 84, 95, aa, d3, 60, e1, 26, 3f, 7c, 6d, e2, eb, d8, 39, de, d7, 74, 45, 1a, 03, 50, 91, 96, 6f, 6c, 1d, 52, 1b, c8, e9, 4e, 07, 64, f5, 8a, 33, 40, 41, 06, 9f, 5c, cd, c2, 4b, b8, 99, be, 37, 54, a5, fa, 63, 30, f1, 76, cf, 4c, 7d, 32, 7b, a8, 49, 2e, 67, 44, 55, 6a, 93, 20, a1, e6, ff, 3c, 2d, a2, ab, 98, f9, 9e, 97, 34, 05, da, c3, 10, 51, 56, 2f, 2c, dd, 12, db, 88, a9, 0e, c7, 24, b5, 4a, f3, + +Builtin Random: +=== Found failing case at depth 1 after 532 ticks: Fail only at large value === +0: Builtin_Random 0xe81de362a1f9f35f +1: 'Fail only at large value' fails diff --git a/Examples/Sorter/Makefile b/Examples/Sorter/Makefile new file mode 100644 index 0000000..8b72bf3 --- /dev/null +++ b/Examples/Sorter/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) Sorter.hs + +clean: + rm -rf *.o *.hi Sorter Sorter-Verilog diff --git a/work/BuggySuite/Sorter.hs b/Examples/Sorter/Sorter.hs similarity index 96% rename from work/BuggySuite/Sorter.hs rename to Examples/Sorter/Sorter.hs index 8ac899e..0458c89 100644 --- a/work/BuggySuite/Sorter.hs +++ b/Examples/Sorter/Sorter.hs @@ -107,7 +107,7 @@ allDifferent (x:xs) = allDifferent xs .&. different xs testBench :: Module () testBench = do - let prop_Sorted = ForallList 27 \(xs :: [Bit 1]) -> Assert (xs.sort3.isSorted) + let prop_Sorted = ForallList 22 \(xs :: [Bit 1]) -> Assert (xs.sort3.isSorted) -- Useful for forcing error to be found for list with unique values: --let prop_Sorted = ForallList 8 \(xs :: [Bit 3]) -> Assert' (xs.allDifferent.inv .|. xs.sort2.isSorted) (display_ $ xs.sort2) @@ -121,4 +121,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "Sorter-Verilog/" diff --git a/Examples/Sorter/Sorter.out b/Examples/Sorter/Sorter.out new file mode 100644 index 0000000..6ae9b3e --- /dev/null +++ b/Examples/Sorter/Sorter.out @@ -0,0 +1 @@ +--All tests passed at time 4194303-- diff --git a/Examples/Sums/Makefile b/Examples/Sums/Makefile new file mode 100644 index 0000000..45177b8 --- /dev/null +++ b/Examples/Sums/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) Sums.hs + +clean: + rm -rf *.o *.hi Sums Sums-Verilog diff --git a/work/BuggySuite/Sums.hs b/Examples/Sums/Sums.hs similarity index 75% rename from work/BuggySuite/Sums.hs rename to Examples/Sums/Sums.hs index 8f16317..000f7ab 100644 --- a/work/BuggySuite/Sums.hs +++ b/Examples/Sums/Sums.hs @@ -3,8 +3,8 @@ import BlarneyCheck testBench :: Module () testBench = do - let prop_Associativity = Forall \(x :: Bit 10) -> Forall \y -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) - let prop_Commutativity = Forall \(x :: Bit 15) -> Forall \y -> Assert (x + y .==. y + x) + let prop_Associativity = Forall \(x :: Bit 8) -> Forall \y -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) + let prop_Commutativity = Forall \(x :: Bit 12) -> Forall \y -> Assert (x + y .==. y + x) -- Flawed assumption of Commutativity of subtraction: --let prop_SubComm = Forall \(x :: Bit 15) -> Forall \y -> Assert (x - y .==. y - x) @@ -20,4 +20,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "Sums-Verilog/" diff --git a/Examples/Sums/Sums.out b/Examples/Sums/Sums.out new file mode 100644 index 0000000..0d4f93b --- /dev/null +++ b/Examples/Sums/Sums.out @@ -0,0 +1 @@ +--All tests passed at time 16777215-- diff --git a/Examples/Sums_Parallel/Makefile b/Examples/Sums_Parallel/Makefile new file mode 100644 index 0000000..a9ee0a3 --- /dev/null +++ b/Examples/Sums_Parallel/Makefile @@ -0,0 +1,6 @@ +.PHONY: all +all: + blcc $(BLC_FLAGS) Sums_Parallel.hs + +clean: + rm -rf *.o *.hi Sums_Parallel Sums_Parallel-Verilog diff --git a/work/BuggySuite/Sums_Parallel.hs b/Examples/Sums_Parallel/Sums_Parallel.hs similarity index 84% rename from work/BuggySuite/Sums_Parallel.hs rename to Examples/Sums_Parallel/Sums_Parallel.hs index ca1d6c7..51c2ac9 100644 --- a/work/BuggySuite/Sums_Parallel.hs +++ b/Examples/Sums_Parallel/Sums_Parallel.hs @@ -30,10 +30,10 @@ instance KnownNat n => Generator (Upper n) where testBench :: Module () testBench = do - let prop_Associativity1 = Forall \(Lower x) -> Forall \(y :: Bit 10) -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) - let prop_Associativity2 = Forall \(Upper x) -> Forall \(y :: Bit 10) -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) - let prop_Commutativity1 = Forall \(Lower x) -> Forall \(y :: Bit 15) -> Assert (x + y .==. y + x) - let prop_Commutativity2 = Forall \(Upper x) -> Forall \(y :: Bit 15) -> Assert (x + y .==. y + x) + let prop_Associativity1 = Forall \(Lower x) -> Forall \(y :: Bit 8) -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) + let prop_Associativity2 = Forall \(Upper x) -> Forall \(y :: Bit 8) -> Forall \z -> Assert ((x + y) + z .==. x + (y + z)) + let prop_Commutativity1 = Forall \(Lower x) -> Forall \(y :: Bit 12) -> Assert (x + y .==. y + x) + let prop_Commutativity2 = Forall \(Upper x) -> Forall \(y :: Bit 12) -> Assert (x + y .==. y + x) let properties = [ ("Associativity1", prop_Associativity1) @@ -49,4 +49,4 @@ testBench = do -- Code generation main :: IO () -main = writeVerilogTop testBench "top" "Out-Verilog/" \ No newline at end of file +main = writeVerilogTop testBench "top" "Sums_Parallel-Verilog/" diff --git a/Examples/Sums_Parallel/Sums_Parallel.out b/Examples/Sums_Parallel/Sums_Parallel.out new file mode 100644 index 0000000..6cc8c43 --- /dev/null +++ b/Examples/Sums_Parallel/Sums_Parallel.out @@ -0,0 +1 @@ +--All tests passed at time 8388607-- diff --git a/Examples/Synthesizable/.gitignore b/Examples/Synthesizable/.gitignore new file mode 100644 index 0000000..25df70c --- /dev/null +++ b/Examples/Synthesizable/.gitignore @@ -0,0 +1,24 @@ + +/*.rpt +/*.msg +/*.summary +/*.sld +/*.sopcinfo +/*.jdi +/c5_pin_model_dump.txt +/*.pin +/*.done +/*.qws +/*.sof +/*.csv +/*.qws +/*.smsg +/*.qdf +**/dse* +**/db +**/incremental_db +**/SoC +**/.qsys_edit +**/reconfig_mif +/*.mif + diff --git a/work/CheckFPGA_ActoraStack/BlarneyComponent.v b/Examples/Synthesizable/BlarneyComponent.v similarity index 100% rename from work/CheckFPGA_ActoraStack/BlarneyComponent.v rename to Examples/Synthesizable/BlarneyComponent.v diff --git a/work/CheckFPGA_ActoraStack/Blarney_hw.tcl b/Examples/Synthesizable/Blarney_hw.tcl similarity index 100% rename from work/CheckFPGA_ActoraStack/Blarney_hw.tcl rename to Examples/Synthesizable/Blarney_hw.tcl diff --git a/work/CheckFPGA_ActoraStack/BlockRAM.v b/Examples/Synthesizable/BlockRAM.v similarity index 100% rename from work/CheckFPGA_ActoraStack/BlockRAM.v rename to Examples/Synthesizable/BlockRAM.v diff --git a/work/CheckFPGA_ActoraStack/BlockRAMTrueDual.v b/Examples/Synthesizable/BlockRAMTrueDual.v similarity index 100% rename from work/CheckFPGA_ActoraStack/BlockRAMTrueDual.v rename to Examples/Synthesizable/BlockRAMTrueDual.v diff --git a/work/CheckFPGA_ActoraStack/JTAGUART.v b/Examples/Synthesizable/JTAGUART.v similarity index 100% rename from work/CheckFPGA_ActoraStack/JTAGUART.v rename to Examples/Synthesizable/JTAGUART.v diff --git a/work/CheckFPGA_CPU/Makefile b/Examples/Synthesizable/Makefile similarity index 89% rename from work/CheckFPGA_CPU/Makefile rename to Examples/Synthesizable/Makefile index 5539011..07b688c 100644 --- a/work/CheckFPGA_CPU/Makefile +++ b/Examples/Synthesizable/Makefile @@ -2,21 +2,20 @@ ifndef QUARTUS_ROOTDIR $(error Please set QUARTUS_ROOTDIR) endif -.PHONY: one -one: - make -C Src +%.sof: + make -C Src Top-Verilog/$*.v qsys-generate -syn SoC.qsys quartus_sh --flow compile SoCKitTop.qpf -.PHONY: dse -dse: - make -C Src +%.dse: + make -C Src Top-Verilog/$*.v qsys-generate -syn SoC.qsys - "../../Temp/copy_bram_files.sh" & + "./copy_bram_files.sh" & quartus_dse SoCKitTop.qpf \ --num-seeds 15 \ --launcher local \ --num-concurrent 4 + .PHONY: report report: quartus_dse SoCKitTop.qpf --report utilization diff --git a/work/CheckFPGA_ActoraStack/SoC.qsys b/Examples/Synthesizable/SoC.qsys similarity index 100% rename from work/CheckFPGA_ActoraStack/SoC.qsys rename to Examples/Synthesizable/SoC.qsys diff --git a/work/CheckFPGA_ActoraStack/SoCKitTop.qpf b/Examples/Synthesizable/SoCKitTop.qpf similarity index 100% rename from work/CheckFPGA_ActoraStack/SoCKitTop.qpf rename to Examples/Synthesizable/SoCKitTop.qpf diff --git a/work/CheckFPGA_ActoraStack/SoCKitTop.qsf b/Examples/Synthesizable/SoCKitTop.qsf similarity index 100% rename from work/CheckFPGA_ActoraStack/SoCKitTop.qsf rename to Examples/Synthesizable/SoCKitTop.qsf diff --git a/work/CheckFPGA_ActoraStack/SoCKitTop.sdc b/Examples/Synthesizable/SoCKitTop.sdc similarity index 100% rename from work/CheckFPGA_ActoraStack/SoCKitTop.sdc rename to Examples/Synthesizable/SoCKitTop.sdc diff --git a/work/CheckFPGA_ActoraStack/SoCKitTop.v b/Examples/Synthesizable/SoCKitTop.v similarity index 100% rename from work/CheckFPGA_ActoraStack/SoCKitTop.v rename to Examples/Synthesizable/SoCKitTop.v diff --git a/work/CheckFPGA_ActoraStack/Src/Main.hs b/Examples/Synthesizable/Src/ActoraStack.hs similarity index 100% rename from work/CheckFPGA_ActoraStack/Src/Main.hs rename to Examples/Synthesizable/Src/ActoraStack.hs diff --git a/work/CheckFPGA_BRAMStack/Src/Main.hs b/Examples/Synthesizable/Src/BRAMStack.hs similarity index 100% rename from work/CheckFPGA_BRAMStack/Src/Main.hs rename to Examples/Synthesizable/Src/BRAMStack.hs diff --git a/work/CheckFPGA_CPU/Src/Main.hs b/Examples/Synthesizable/Src/CPU.hs similarity index 100% rename from work/CheckFPGA_CPU/Src/Main.hs rename to Examples/Synthesizable/Src/CPU.hs diff --git a/work/CheckFPGA_FirstHot/Src/Main.hs b/Examples/Synthesizable/Src/FirstHot.hs similarity index 100% rename from work/CheckFPGA_FirstHot/Src/Main.hs rename to Examples/Synthesizable/Src/FirstHot.hs diff --git a/Examples/Synthesizable/Src/Makefile b/Examples/Synthesizable/Src/Makefile new file mode 100644 index 0000000..748a940 --- /dev/null +++ b/Examples/Synthesizable/Src/Makefile @@ -0,0 +1,8 @@ +%.bin: %.hs + blcc -i"./../../$*" $< -o $@ +Top-Verilog/%.v: %.bin + ./$< + #cp $@ Top-Verilog/Top.v ?? + +clean: + rm -rf *.o *.hi *.bin Top-Verilog diff --git a/work/CheckFPGA_Sorter/Src/Main.hs b/Examples/Synthesizable/Src/Sorter.hs similarity index 100% rename from work/CheckFPGA_Sorter/Src/Main.hs rename to Examples/Synthesizable/Src/Sorter.hs diff --git a/work/CheckFPGA_Sums/Src/Main.hs b/Examples/Synthesizable/Src/Sums.hs similarity index 100% rename from work/CheckFPGA_Sums/Src/Main.hs rename to Examples/Synthesizable/Src/Sums.hs diff --git a/work/CheckFPGA_Sums_Parallel/Src/Main.hs b/Examples/Synthesizable/Src/Sums_Parallel.hs similarity index 100% rename from work/CheckFPGA_Sums_Parallel/Src/Main.hs rename to Examples/Synthesizable/Src/Sums_Parallel.hs diff --git a/Temp/copy_bram_files.sh b/Examples/Synthesizable/copy_bram_files.sh similarity index 100% rename from Temp/copy_bram_files.sh rename to Examples/Synthesizable/copy_bram_files.sh diff --git a/work/Haskell/BlarneyCheck.hs b/Haskell/BlarneyCheck.hs similarity index 53% rename from work/Haskell/BlarneyCheck.hs rename to Haskell/BlarneyCheck.hs index 628e9b9..d594371 100644 --- a/work/Haskell/BlarneyCheck.hs +++ b/Haskell/BlarneyCheck.hs @@ -7,11 +7,11 @@ Stability : experimental This is the top-level of library. -} module BlarneyCheck ( - module Core.Check -, module Core.Property -, module Core.Generator + module BlarneyCheck.Check +, module BlarneyCheck.Property +, module BlarneyCheck.Generator ) where -import Core.Check -import Core.Generator -import Core.Property \ No newline at end of file +import BlarneyCheck.Check +import BlarneyCheck.Generator +import BlarneyCheck.Property diff --git a/work/Haskell/Core/Check.hs b/Haskell/BlarneyCheck/Check.hs similarity index 97% rename from work/Haskell/Core/Check.hs rename to Haskell/BlarneyCheck/Check.hs index 010e5f8..01f02ae 100644 --- a/work/Haskell/Core/Check.hs +++ b/Haskell/BlarneyCheck/Check.hs @@ -1,4 +1,4 @@ -module Core.Check +module BlarneyCheck.Check ( checkPure , checkPureFPGA , check @@ -8,11 +8,11 @@ module Core.Check import Blarney import Blarney.Queue -import Core.Property -import Core.PureProp -import Core.ImpureProp -import Core.TestBench -import Core.Utils +import BlarneyCheck.Property +import BlarneyCheck.PureProp +import BlarneyCheck.ImpureProp +import BlarneyCheck.TestBench +import BlarneyCheck.Utils -- Use this function for simulation checkPure :: [Property] -> Module (Bit 1, Bit 1) diff --git a/work/Haskell/Core/Generator.hs b/Haskell/BlarneyCheck/Generator.hs similarity index 98% rename from work/Haskell/Core/Generator.hs rename to Haskell/BlarneyCheck/Generator.hs index b29a4cb..6098cfd 100644 --- a/work/Haskell/Core/Generator.hs +++ b/Haskell/BlarneyCheck/Generator.hs @@ -12,7 +12,7 @@ {-# LANGUAGE AllowAmbiguousTypes #-} {-# LANGUAGE GADTs #-} -module Core.Generator +module BlarneyCheck.Generator ( SizedBits(..) , Generator (..) , RandBits (..) @@ -58,4 +58,4 @@ instance {-# OVERLAPPABLE #-} (SizedBits b, KnownNat i, KnownNat s) => Generator in unpack $ pack current .*. (constant a) .+. 1 isFinal current = pack (initial :: RandBits b (Seed i s)) .==. pack (next current) range = 2^valueOf @(SizeOf b) - \ No newline at end of file + diff --git a/work/Haskell/Core/ImpureProp.hs b/Haskell/BlarneyCheck/ImpureProp.hs similarity index 98% rename from work/Haskell/Core/ImpureProp.hs rename to Haskell/BlarneyCheck/ImpureProp.hs index 992064e..e7c6662 100644 --- a/work/Haskell/Core/ImpureProp.hs +++ b/Haskell/BlarneyCheck/ImpureProp.hs @@ -2,15 +2,15 @@ {-# LANGUAGE FlexibleInstances #-} {-# LANGUAGE RankNTypes #-} -module Core.ImpureProp where +module BlarneyCheck.ImpureProp where import Blarney import Blarney.Recipe (runRecipeOn) import Blarney.Queue import Blarney.Core.Utils -import Core.Generator -import Core.Property -import Core.TestBench +import BlarneyCheck.Generator +import BlarneyCheck.Property +import BlarneyCheck.TestBench -- Standard imports import Data.Proxy diff --git a/work/Haskell/Core/Property.hs b/Haskell/BlarneyCheck/Property.hs similarity index 88% rename from work/Haskell/Core/Property.hs rename to Haskell/BlarneyCheck/Property.hs index 19566ff..05164ac 100644 --- a/work/Haskell/Core/Property.hs +++ b/Haskell/BlarneyCheck/Property.hs @@ -2,14 +2,14 @@ {-# LANGUAGE FlexibleInstances #-} {-# LANGUAGE RankNTypes #-} -module Core.Property +module BlarneyCheck.Property ( Property(..) , Prop (..) ) where import Blarney import Blarney.Recipe -import Core.Generator +import BlarneyCheck.Generator type Property = (String, Prop) diff --git a/work/Haskell/Core/PureProp.hs b/Haskell/BlarneyCheck/PureProp.hs similarity index 96% rename from work/Haskell/Core/PureProp.hs rename to Haskell/BlarneyCheck/PureProp.hs index e360ebb..d21eb4b 100644 --- a/work/Haskell/Core/PureProp.hs +++ b/Haskell/BlarneyCheck/PureProp.hs @@ -2,12 +2,12 @@ {-# LANGUAGE FlexibleInstances #-} {-# LANGUAGE RankNTypes #-} -module Core.PureProp where +module BlarneyCheck.PureProp where import Blarney -import Core.Generator -import Core.Property -import Core.TestBench +import BlarneyCheck.Generator +import BlarneyCheck.Property +import BlarneyCheck.TestBench propertyToPureTB :: Property -> Module PureTestBench diff --git a/work/Haskell/Core/TestBench.hs b/Haskell/BlarneyCheck/TestBench.hs similarity index 98% rename from work/Haskell/Core/TestBench.hs rename to Haskell/BlarneyCheck/TestBench.hs index 9fa26a2..dfc6395 100644 --- a/work/Haskell/Core/TestBench.hs +++ b/Haskell/BlarneyCheck/TestBench.hs @@ -2,7 +2,7 @@ {-# LANGUAGE FlexibleInstances #-} {-# LANGUAGE RankNTypes #-} -module Core.TestBench where +module BlarneyCheck.TestBench where import Blarney diff --git a/work/Haskell/Core/Utils.hs b/Haskell/BlarneyCheck/Utils.hs similarity index 97% rename from work/Haskell/Core/Utils.hs rename to Haskell/BlarneyCheck/Utils.hs index ed66984..77157e3 100644 --- a/work/Haskell/Core/Utils.hs +++ b/Haskell/BlarneyCheck/Utils.hs @@ -18,12 +18,12 @@ {-# LANGUAGE AllowAmbiguousTypes #-} {-# LANGUAGE GADTs #-} -module Core.Utils where +module BlarneyCheck.Utils where import Blarney import Blarney.Queue -import Core.Generator -import Core.Property +import BlarneyCheck.Generator +import BlarneyCheck.Property import Data.Char (ord) diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..3ff27b4 --- /dev/null +++ b/Makefile @@ -0,0 +1,8 @@ +top: + +.PHONY: clean +clean: + rm -f Haskell/*.hi Haskell/*.o + rm -f Haskell/Blarneycheck/*.hi Haskell/Blarneycheck/*.o + make -C Examples clean + diff --git a/README.md b/README.md index b132d43..5f13340 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,37 @@ # blarneycheck -Automatic testing of Blarney programs. +--- + +An exhaustive property-based testing library for Blarney. + +Make sure to use the `--recursive` flag to include the Blarney repo: +```sh +> git clone --recursive https://github.com/JonasAlaif/blarneycheck.git +``` +Alternatively set the `BLARNEY_ROOT` environment variable to point at a copy of Blarney. + +The library resides in the 'Haskell' directory and can be imported in any Haskell code: +```hs +import BlarneyCheck +``` + +To compile a module which imports BlarneyCheck use the modified `blcc` script, instead of `blc`. +Where `blcc` stands for *BlarneyCheck compiler*. + +Example modules and associated test benches are provided in the 'Examples' directory. +These can be simulated as a regression test with: +```sh +> ./Test/test.sh +``` + +Simulation requires GHC 8.6.5 and Verilator to be installed. The examples are also given +as synthesis ready in the 'Synthesizable' directory. Simply: +```sh +> cd Examples/Synthesizable +> make .sof +``` +This synthesizes the module and test bench. Synthesis requires Quartus to be installed +on the system. To program an FPGA with the test bench run: +```sh +> make download-sof && nios2-terminal +``` + diff --git a/Scripts/blcc b/Scripts/blcc new file mode 100755 index 0000000..cdf191a --- /dev/null +++ b/Scripts/blcc @@ -0,0 +1,9 @@ +#! /usr/bin/env bash + +BC_ROOT="$(dirname "$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )")" +if [ -z "$BLARNEY_ROOT" ]; then + export BLARNEY_ROOT="$BC_ROOT/blarney" +fi + +"$BLARNEY_ROOT/Scripts/blc" -I"$BC_ROOT/Haskell" -i"$BC_ROOT/Haskell" $@ + diff --git a/Temp/BlarneycheckTodo.txt b/Temp/BlarneycheckTodo.txt deleted file mode 100644 index eb9ef3f..0000000 --- a/Temp/BlarneycheckTodo.txt +++ /dev/null @@ -1,47 +0,0 @@ -Forall(Bits a => a -> Prop) -Forall(KnownNat n => Bit n -> Prop) -ForallList(Int -> [Bit 8] -> Prop) - - -prop = ForAllList \xs -> isSOrted(sort xs) - -widthOf :: KnownNat n => n -> int -sizeOf :: Bits a => a -> int - -Instantiate prop just once - -class Serial a - series :: Int -> [a] - -------- - -data ShowList where - ShowList :: Show a => [a] - -data Gen a = - -------- - -Make sequential check work with Bits (Serial) ---Create sorter (buggy) and check lists -Allow choice of seq or par check - -------- - -Create sorter (buggy) and check lists -Streams? - -------- - -Get max size of input -Zero one principle of sorters -https://github.com/POETSII/actora/blob/master/rtl/Stack.hs -Look into koens thesis tutorial for examples - - Rotate left/right - - Matrix/Vector operations - ---------- - -Implement for FPGA testing -Generator - diff --git a/Temp/ReadingList.txt b/Temp/ReadingList.txt deleted file mode 100644 index dd254e3..0000000 --- a/Temp/ReadingList.txt +++ /dev/null @@ -1,3 +0,0 @@ -"How to Specify it! A Guide to Writing Properties of Pure Functions" https://www.tfp2019.org/resources/tfp2019-how-to-specify-it.pdf - -"Testing monadic code withe QuickCheck" https://dl.acm.org/citation.cfm?id=636527 diff --git a/Temp/SimulateBlarney.sh b/Temp/SimulateBlarney.sh deleted file mode 100755 index 5df15ab..0000000 --- a/Temp/SimulateBlarney.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/bash -# Run from the work directory in BlarneyCheck - -FILE=${1?Error: no file given} -FILENAME=$(basename "$FILE") -FILEDIR=$(dirname "$FILE") -if [[ $* == *--eval* ]] -then - OUTDIR="Evaluation" -else - OUTDIR="Simulation" -fi - -if ! [[ -d "/opt/ghc/bin" || -x "$(command -v ghc)" ]]; then - echo "Installing ghc files in /opt/ghc/bin..." - sudo add-apt-repository -y ppa:hvr/ghc - sudo apt-get update - sudo apt-get install -y ghc-8.6.5 -fi - -pkgs='verilator' -if ! dpkg -s $pkgs >/dev/null 2>&1; then - sudo apt-get install $pkgs -fi - -echo "Running: $FILE" - -PATH="/opt/ghc/bin:$PATH" BLARNEY_ROOT="blarney" "blarney/Scripts/blc" "$FILE" - -cd $FILEDIR -EXECUTABLE=$(basename $FILENAME .hs) -if [ -f "./$EXECUTABLE" ]; then - ./$EXECUTABLE - cd Out-Verilog - make -s - echo "Executed $EXECUTABLE with result of:" - mkdir -p ../Results/$OUTDIR/$EXECUTABLE - (time ./top | head -n -1) 2>&1 | tee "../Results/$OUTDIR/$EXECUTABLE/output_$(date +"%Y_%d_%m_%H_%M_%S").txt" - - cd .. -fi - -rm -rf *.o *.hi "$FILEDIR/$EXECUTABLE" Out-Verilog diff --git a/Temp/proj_wc.sh b/Temp/proj_wc.sh deleted file mode 100755 index 7369a09..0000000 --- a/Temp/proj_wc.sh +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/bash - -cd /home/jonas/Part_II_Project/blarneycheck/work/ -wc -l {Check/*.hs,BuggySuite/{ActoraStack,BRAMStack,CPU,FirstHot,MemAddr,RandomCheck,Sums,Sums_Parallel}.hs,CheckFPGA_*/Src/*.hs} diff --git a/Temp/simulate_all.sh b/Temp/simulate_all.sh deleted file mode 100755 index 8b36999..0000000 --- a/Temp/simulate_all.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/bash - -cd /home/jonas/Part_II_Project/blarneycheck/work -examples="ActoraStack BRAMStack CPU FirstHot Sorter Sums Sums_Parallel" - -for i in {1..16} -do - for ex in $examples - do - /home/jonas/Part_II_Project/blarneycheck/Temp/SimulateBlarney.sh "BuggySuite/$ex.hs" "--eval" - done -done - -cd BuggySuite/Results/Evaluation -for ex in $examples -do - cd "$ex" - printf "\n$ex:\n" - ls -rt ./ | xargs grep -rohP '(?<=user\t).*' - cd .. -done diff --git a/Temp/synthesize_all.sh b/Temp/synthesize_all.sh deleted file mode 100755 index e9ef039..0000000 --- a/Temp/synthesize_all.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/bash - -COMMAND=${1:-} - -[ -f "${QUARTUS_ROOTDIR}/adm/qenv.sh" ] && source "${QUARTUS_ROOTDIR}/adm/qenv.sh" -[ -d "${QSYS_ROOTDIR}" ] && export PATH="${QSYS_ROOTDIR}:${PATH}" - -cd /home/jonas/Part_II_Project/blarneycheck/work/CheckFPGA_ActoraStack/ -printf "ActoraStack:\n" -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nBRAMStack:\n" -cd ../CheckFPGA_BRAMStack/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nCPU:\n" -cd ../CheckFPGA_CPU/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nFirstHot\n" -cd ../CheckFPGA_FirstHot/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nSorter\n" -cd ../CheckFPGA_Sorter/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nSums\n" -cd ../CheckFPGA_Sums/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - -printf "\n\nSums_Parallel:\n" -cd ../CheckFPGA_Sums_Parallel/ -make $COMMAND -quartus_dse SoCKitTop.qpf --report fmax_summary --report-format csv --report-file report_fmax.csv -quartus_dse SoCKitTop.qpf --report utilization --report-format csv --report-file report_util.csv - diff --git a/Test/test.sh b/Test/test.sh new file mode 100755 index 0000000..4419cb5 --- /dev/null +++ b/Test/test.sh @@ -0,0 +1,22 @@ +#! /usr/bin/env bash + +# Run regression tests + +EXAMPLES=( + ActoraStack + BRAMStack + CPU + FirstHot + MemAddr + RandomCheck + Sorter + Sums + Sums_Parallel +) + +BC_ROOT="$(dirname "$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )")" +if [ -z "$BLARNEY_ROOT" ]; then + export BLARNEY_ROOT="$BC_ROOT/blarney" +fi + +EXAMPLES="${EXAMPLES[@]}" TESTING_ROOT=$BC_ROOT "$BLARNEY_ROOT/Test/test.sh" $@ diff --git a/blarney b/blarney new file mode 160000 index 0000000..976f24e --- /dev/null +++ b/blarney @@ -0,0 +1 @@ +Subproject commit 976f24e12f3ce0a353b667021ac57975a9fb2a7d diff --git a/diss/diss_backups/Part II Project Dissertation 04_5.zip b/diss/diss_backups/Part II Project Dissertation 04_5.zip deleted file mode 100644 index 8189f0d..0000000 Binary files a/diss/diss_backups/Part II Project Dissertation 04_5.zip and /dev/null differ diff --git a/diss/diss_backups/Part II Project Dissertation 09_5.zip b/diss/diss_backups/Part II Project Dissertation 09_5.zip deleted file mode 100644 index 4ffb018..0000000 Binary files a/diss/diss_backups/Part II Project Dissertation 09_5.zip and /dev/null differ diff --git a/diss/diss_backups/Part II Project Dissertation 22_4.zip b/diss/diss_backups/Part II Project Dissertation 22_4.zip deleted file mode 100644 index ce4c4bf..0000000 Binary files a/diss/diss_backups/Part II Project Dissertation 22_4.zip and /dev/null differ diff --git a/diss/diss_backups/Part II Project Dissertation 28_4.zip b/diss/diss_backups/Part II Project Dissertation 28_4.zip deleted file mode 100644 index b27f61a..0000000 Binary files a/diss/diss_backups/Part II Project Dissertation 28_4.zip and /dev/null differ diff --git a/diss/diss_backups/jf613.pdf b/diss/diss_backups/jf613.pdf deleted file mode 100644 index f7c52f5..0000000 Binary files a/diss/diss_backups/jf613.pdf and /dev/null differ diff --git a/proposal/1_project_selection_form.txt b/proposal/1_project_selection_form.txt deleted file mode 100644 index ce6954d..0000000 --- a/proposal/1_project_selection_form.txt +++ /dev/null @@ -1,73 +0,0 @@ -Subject: Phase 1 - Fiala: Property-based testing for hardware - -Phase 1 Project Selection Status Report - -Name: Jonas Fiala - -College: Trinity Hall - -User Identifier: jf613 - -Director of Studies: Simon Moore & Hatice Gunes - -Please complete 1, 2 and 3 below. - -1. Please write 100 words on your current project ideas. - -QuickCheck and SmallCheck are existing testing libraries that -encourage lightweight formal specification of software through -the reward of automatic testing and small counter-examples. -The idea of this project would be to apply a similar approach -to a HDL. -The HDL of choice would be Blarney (https://github.com/mn416/blarney) -for Haskell. This is similar to what BlueCheck does, but with the -novelty of verification in an open source context (Blarney) and -using bounded exhaustive testing rather than random testing. -The evaluation criteria would be defined as building a version of -SmallCheck that can test combinatorial logic circuits; finding bugs -in a suite of example buggy circuits and properties. I could then -measure the size of counter-examples found, measure time taken to -find counter examples and compare that to the time taken on a test -rig synthesized to an FPGA. -There are many further possibilities beyond the success criteria -for this project: - - Build a SMT solver backend for Blarney and compare speeds - - Extend to allow for random testing (like QuickCheck) - - Extend to work with sequential logic (like BlueCheck) - - - -2. Please list names of potential project supervisors. - -Matthew Naylor - - - -3. Is there any chance that your project will involve any -computing resources other than the Computing Service's MCS and -software that is already installed there, for example: your own -machine, machines in College, special peripherals, imported -software packages, special hardware, network access, substantial -extra disc space on the MCS. - -If so indicate below what, and what it is needed for. - - - Haskell: require ghc version 8.6.1 for Blarney, but the default - apt get ghc installs version 8.0.2 (this is what is on MCS) so must - download manually. - - CL account: can access required version of ghc if necessary, also to - use Bluespec/BlueCheck if necessary. - - Blarney: downloaded with git clone. - - Machines in College - similar to MCS machines. - - FPGA: for synthesizing testing rigs. - - I also plan to use my own laptop and computer - My laptop: 2.30 GHz CPU, 8 GB RAM, 118 GB Solid-state disk for OS - and 447 GB Solid-state disk for data, Windows OS with Ubuntu VM - My computer: 3.50 GHz CPU, 8 GB RAM, 256 GB Solid-state disk for OS - and 1 TB Solid-state disk for data, Windows OS with Ubuntu VM - My contingency plans against data loss are that everything - will be held under git on Github with daily checkpoints to - my Google Drive and also weekly to USB Flash Drive kept only for - that purpose. - My contingency plans against hardware/software failure are - that I can easily transition my work to the MCS/CL machines \ No newline at end of file diff --git a/proposal/2_project_proposal_draft.tex b/proposal/2_project_proposal_draft.tex deleted file mode 100644 index 42df41e..0000000 --- a/proposal/2_project_proposal_draft.tex +++ /dev/null @@ -1,304 +0,0 @@ -\documentclass[UKenglish, 12pt]{article} -\usepackage{a4wide} -\usepackage{isodate} - -\newcommand{\al}{$<$} -\newcommand{\ar}{$>$} - -\parindent 0pt -\parskip 6pt - -\begin{document} - -\thispagestyle{empty} - -\rightline{\large{Jonas Fiala}} -\medskip -\rightline{\large{Trinity Hall}} -\medskip -\rightline{\large{jf613}} - -\vfil - -\centerline{\large Part II Project Proposal} -\vspace{0.4in} -\centerline{\Large\bf Property-based Testing for Hardware} -\vspace{0.3in} -\centerline{\large{October 2019}} - -\vfil - -{\bf Project Originator:} \al\emph{What to put here?}\ar - -\vspace{0.1in} - -{\bf Resources Required:} See attached Project Resource Form - -\vspace{0.5in} - -{\bf Project Supervisor:} {Matthew Naylor} - -\vspace{0.2in} - -{\bf Signature:} - -\vspace{0.5in} - -{\bf Director of Studies:} {Simon Moore and Hatice Gunes} - -\vspace{0.2in} - -{\bf Signatures:} - -\vspace{0.5in} - -{\bf Overseers:} {Pietro Li\'o} and {Robert Mullins} - -\vspace{0.2in} - -{\bf Signatures:} - -\vfil -\eject - - -\al\emph{Some comments are included, styled in this fashion, which -won't be in the final Proposal!}\ar - -\section*{Introduction and Description of the Work} - -Test rigs are common when developing hardware and so many techniques have -been developed for automatic testing and generation of test cases. Property-based -testing is a useful and now commonplace idea in automatic testing. - -There has been much research regarding automatic testing for software design. -\begin{description} - -\item [QuickCheck] implements random testing with a given or user specified distribution~\cite{QuickCheck} - -\item [SmallCheck] implements exhaustive testing up to some depth~\cite{SmallCheck} - -\end{description} -Both are existing testing libraries that encourage lightweight formal specification -of software through the reward of automatic testing and small counter-examples. -More recently this idea has also been applied to hardware. -\begin{description} - -\item [BlueCheck] implements random testing \`a la QuickCheck but for a HDL (Bluespec)~\cite{BlueCheck} - -\end{description} - -Yet few automatic testing libraries have been created for open source HDLs, so this -project will propose to bring bounded exhaustive testing to an exciting new -Haskell library for hardware description; Blarney (https://github.com/mn416/blarney). - -\al\emph{What else to add? Somehow bring \cite{Koen} into this?}\ar - - - - -\section*{Resources Required} - -\begin{description} - -\item [Haskell:] require ghc version 8.6.1 for Blarney, but the default -apt get ghc installs version 8.0.2 (this is what is on MCS) so must -download manually. - -\item [CL account:] can access required version of ghc if necessary, also to -use Bluespec/BlueCheck if necessary. - -\item [Blarney:] downloaded with git clone. - -\item [FPGA:] for synthesizing testing rigs. - -\item [Machines in College:] similar to MCS machines, only needed if personal -hardware fails. - -\item [Personal laptop and computer:]- - -\begin{description} - -\item [My laptop:] 2.30 GHz CPU, 8 GB RAM, 118 GB Solid-state disk for OS -and 447 GB Solid-state disk for data, Windows OS with Ubuntu VM - -\item [My computer:] 3.50 GHz CPU, 16 GB RAM, 256 GB Solid-state disk for OS -and 1 TB Solid-state disk for data, Windows OS with Ubuntu VM - -\item [Contingency plans:] My contingency plans against data loss are that everything -will be held under git on GitHub with daily checkpoints to -my Google Drive and also weekly to USB Flash Drive kept only for -that purpose. -My contingency plans against hardware/software failure are -that I can easily transition my work to the MCS/CL machines - -\end{description} - -\end{description} - - -\section*{Starting Point} - -I have basic prior knowledge, from taking the \textbf{Computer Design} course in \textbf{Part IB} and the \textbf{Digital Electronics} course in \textbf{Part IA} including the practicals for both. Therefore an important part of the project will be learning to use the required tools. - - -\section*{Substance and Structure of the Project} - -The aim of the project is to build a Haskell library for automatic testing -of modules written in Blarney. I would primarily draw inspiration from -SmallCheck~\cite{SmallCheck} and apply it to a HDL, this would mean -bounded exhaustive testing. - -There are many further possibilities beyond the success criteria for this -project: -\begin{description} - -\item [Synthesis] of a test rig to an FPGA and compare speeds against a simulated test rig~\cite{BlueCheck} - -\item [Sequential logic] modules could be supported, testing a bounded sequence of inputs~\cite{BlueCheck} - -\item [Random testing] similar to QuickCheck and BlueCheck~\cite{QuickCheck}\cite{BlueCheck} - -\item [Other verification methods] (such as an SMT solver) could be created for Blarney and then compared to the bounded exhaustive testing method \al\emph{Cite?}\ar - -\end{description} - -\begin{thebibliography}{9} - - \bibitem {QuickCheck} - K. Claessen and J. Hughes. \emph{QuickCheck: A Lightweight Tool for Random Testing of Haskell Programs}, in Proceedings of ICFP’2000, (2000) - - \bibitem {Koen} - K. Claessen. \emph{Embedded Languages for Describing and Verifying Hardware}. PhD thesis, Chalmers University of Technology and G\"oteborg University (2001) - - \bibitem {SmallCheck} - C. Runciman, M. Naylor, F. Lindblad. \emph{SmallCheck and Lazy SmallCheck: automatic exhaustive testing for small values}, in Haskell Symposium ’08. pp. 37–48. ACM (2008) - - \bibitem {BlueCheck} - M. Naylor and S. W. Moore. \emph{A Generic Synthesisable Test Bench}, in MEMOCODE 2015, pp. 128–137 (2015) - -\end{thebibliography} - -\section*{Success Criteria} - -The following should be achieved: - -\begin{itemize} - -\item Implement a Haskell library for automatic testing of combinatorial circuits written in Blarney - -\item Devise a suite of example buggy circuits - -\item Measure the proportion of bugs reported and the size of counter-examples found - -\end{itemize} -\al\emph{Should this be more concrete? Can also include synthesis to FPGA as a -success criteria since it will almost certainly be done?}\ar - - -\section*{Timetable and Milestones} - -\subsection*{25th October to 21st November} - -\al\emph{4 weeks * 20\% time (10hrs a week) = 40hrs}\ar - -Research property-based testing for software and also hardware, making sure to -fully understand the related work. Setup and test the SmallCheck/QuickCheck -libraries for Haskell, to better understand how they work and to improve skills -with Haskell. -Learn to use Blarney, building some example circuits as a learning exercise. - -Milestones: Implement small Blarney modules of combinatorial logic. Design -structure of testing framework and type-based generators. - - -\subsection*{22nd November to 5th December} -\al\emph{2 weeks * 50\% time (25hrs a week) = 50hrs}\ar - -Setup BlueCheck and Bluespec to test synthesizing test benches to an -FPGA. -Decide with the help of Matt on final design of the testing library, with -further literature study if necessary. Create the enumerative generators. - -Milestones: Lay out structure necessary to meet the success criteria and -be ready to work on my own over the Christmas vacation. - -\subsection*{6th to 26th December (Christmas vacation)} -\al\emph{2 weeks (+ 1 weeks holiday) * 60\% time (30hrs a week) = 60hrs}\ar - -Complete success criteria, namely: Implement a Haskell library for automatic -testing of combinatorial circuits written in Blarney. If any problems arise -can use second half of Christmas vacation to finish the work, at the cost of -fewer additional features. Otherwise if finished early start work on -Dissertation. - -Milestones: Code satisfies the first point of the success criteria. Introduction -chapter of Dissertation mostly complete. - -\subsection*{27th December to 16th January (Christmas vacation)} -\al\emph{2 weeks (+ 1 weeks holiday) * 60\% time (30hrs a week) = 60hrs}\ar - -Start building additional features as able, with priority for synthesizing test -rigs to an FPGA. Write Preparation chapter of Dissertation and start work on -Implementation chapter. - -Milestones: Synthesized test rig runs on FPGA. First 2 chapters of Dissertation -mostly complete and structure of Implementation chapter laid out. Some of the -proposed additional features complete. - -\subsection*{17th January to 27th February} -\al\emph{6 weeks * 6\% time (3hrs a week) = 18hrs}\ar - -Create progress report and presentation. -Run the library on the example buggy circuits in preparation for Evaluation -chapter. Start of lent term is very intense so use the long time at low intensity -to make small improvements and find any bugs. - -Milestones: Progress report and presentation done. Test data for Evaluation -generated. - -\subsection*{28th February to 12th March} -\al\emph{2 weeks * 40\% time (20hrs a week) = 40hrs}\ar - -Complete all additional features and clean up code. Project should be stable -at this point, with all changes being only minor after this point. - -Milestones: Project is complete and stable to allow writing Dissertation. - -\subsection*{13th March to 23rd April (Easter vacation)} -\al\emph{2 weeks * 60\% time (30hrs a week) = 60hrs}\ar - -Finish up the Introduction and Preparation chapters and write Implementation -chapter. Make only small crucial changes to code (e.g. bug fixes) - -Milestones: First 3 chapters of Dissertation complete. Codebase finalized, -ready for submission. - -\subsection*{13th March to 23rd April (Easter vacation)} -\al\emph{3 weeks (+ 1 week holiday) * 60\% time (30hrs a week) = 90hrs}\ar - -Write Evaluation and Conclusions chapters, running any additional tests to gather -evaluation data if necessary. I can use this time to do additional work on the -project if Timetable has been moved back, otherwise for revision for final exams. - -Milestones: Dissertation finished, ready for submission if necessary. - -\subsection*{24th to 30th April} -\al\emph{1 week * 75\% time = 37.5hrs}\ar - -Review whole project, check the Dissertation, and spend a final few -days on whatever is in greatest need of attention. - -Milestones: Dissertation polished. - -\al\emph{Upper bound of 455.5hrs for project, with EV of about 350hrs}\ar - - -\subsection*{1st to 7th May} -\al\emph{1 week * ?? = up to 50hrs}\ar - -Aim to submit Dissertation a week before the deadline. - -Milestone: Submission of Dissertation. - -\end{document} \ No newline at end of file diff --git a/proposal/3_final_proposal.tex b/proposal/3_final_proposal.tex deleted file mode 100644 index 1e96b2d..0000000 --- a/proposal/3_final_proposal.tex +++ /dev/null @@ -1,302 +0,0 @@ -\documentclass[UKenglish, 12pt]{article} -\usepackage{a4wide} -\usepackage{isodate} -\usepackage{listings} -\lstset{ - literate={~} {$\sim$\,}{1} -} - -\newcommand{\al}{$<$} -\newcommand{\ar}{$>$} - -\parindent 0pt -\parskip 6pt - -\begin{document} - -\thispagestyle{empty} - -\rightline{\large{Jonas Fiala}} -\medskip -\rightline{\large{Trinity Hall}} -\medskip -\rightline{\large{jf613}} - -\vfil - -\centerline{\large Part II Project Proposal} -\vspace{0.4in} -\centerline{\Large\bf Property-based Testing for Hardware} -\vspace{0.3in} -\centerline{\large{October 2019}} - -\vfil - -{\bf Project Originators:} {Matthew Naylor and Jonas Fiala} - -\vspace{0.1in} - -{\bf Resources Required:} See attached Project Resource Form - -\vspace{0.5in} - -{\bf Project Supervisor:} {Matthew Naylor} - -\vspace{0.2in} - -{\bf Signature:} - -\vspace{0.5in} - -{\bf Directors of Studies:} {Simon Moore and Hatice Gunes} - -\vspace{0.2in} - -{\bf Signatures:} - -\vspace{0.5in} - -{\bf Overseers:} {Pietro Li\'o} and {Robert Mullins} - -\vspace{0.2in} - -{\bf Signatures:} - -\vfil -\eject - - -\section*{Introduction and Description of the Work} - -Test benches are common when developing hardware and so many techniques have -been developed for automatic testing and generation of test cases. Property-based -testing requires the designer to specify a set of invariants for the module being tested, this allows automatic testing to check that these invariants always hold, reporting back if that is the case. This is a useful and now commonplace idea in automatic testing. - -Property-based testing has become popular in the software community. Both \textbf{QuickCheck}~\cite{QuickCheck} and \textbf{SmallCheck}~\cite{SmallCheck} are existing testing libraries that encourage lightweight formal specification -of software through the reward of automatic testing and small counter-examples. -Recent work~\cite{BlueCheck} has successfully applied the idea to -hardware development in the Bluespec HDL. - -Hardware verification tools are often commercial products and -expensive, so the open-source community needs new approaches. -This project will continue the work of \textbf{BlueCheck}, but explore some -new avenues. Namely we will use an open-source Bluespec-like HDL~\cite{Blarney} -developed here in the CL, additionally we will use bounded exhaustive testing, -which can can find minimal counterexamples without the need for shrink steps. - - -\section*{Starting Point} - -I have basic prior knowledge, from taking the \textbf{Computer Design} course in \textbf{Part IB} and the \textbf{Digital Electronics} course in \textbf{Part IA} including the practicals for both. Therefore an important part of the project will be learning to use the required tools. - - -\section*{Substance and Structure of the Project} - -The aim of the project is to build a Haskell library for automatic testing -of modules written in Blarney. Primarily I will draw inspiration from SmallCheck~\cite{SmallCheck} -and apply it to a HDL. As such a method using bounded exhaustive testing will -be implemented. This gives a clear demarcation between tested -and untested cases, and also guarantees finding small counterexamples. The work consists -of three main parts, described in the success criteria. - -The project will likely be expanded to achieve some of the additional points mentioned -in the next section, but which ones are chosen will depend on the effectiveness of -the initial implementation. Further options may be discovered when -researching this topic in depth and also implemented. - - -\section*{Success Criteria} - -The following should be achieved: - -\begin{itemize} - -\item Implement a Haskell library for automatic testing of combinatorial circuits written in Blarney - -\item Devise a suite of example properties and buggy circuits, to -evaluate the effectiveness of the library - -\item Measure the proportion of bugs reported and the size of counter-examples found - -\end{itemize} - - -One nice example to test is firstHot (from BlueCheck~\cite{BlueCheck}), which returns a bit-string in which only the least significant non-zero bit of the input bit-string is set: -\begin{lstlisting}[language=Verilog] -// FirstHot implementation to test -function Bit#(n) firstHot(Bit#(n) x) = x & (~x+1); - -// The defining properties that any First Hot function must meet: -// Excatly one bit is set if nonzero, otherwise no bits set -function Bool prop_OneIsHot(Bit#(8) x) = - countOnes(firstHot(x)) == (x == 0 ? 0 : 1); - -// Hot bit in output is also hot in input -function Bool prop_HotBitCommon(Bit#(8) x) = - (x & firstHot(x)) == firstHot(x); - -// No less-significant hot bits in input than that set in output -function Bool prop_HotBitFirst(Bit#(8) x) = - (x & (firstHot(x)-1)) == 0; -\end{lstlisting} - -\vspace{5mm} -Finally there are many further possibilities beyond the success criteria for this -project: -\begin{description} - -\item [Synthesis] of a test bench to an FPGA and compare speeds against a simulated test bench~\cite{BlueCheck} - -\item [Sequential logic] modules could be supported, testing a bounded sequence of inputs~\cite{BlueCheck} - -\item [Random testing] similar to QuickCheck and BlueCheck~\cite{QuickCheck, BlueCheck} - -\item [Other verification methods] (such as an SMT solver) could be created for Blarney and then compared to the bounded exhaustive testing method - -\end{description} - -\begin{thebibliography}{9} - - \bibitem {QuickCheck} - K. Claessen and J. Hughes. \emph{QuickCheck: A Lightweight Tool for Random Testing of Haskell Programs}, in Proceedings of ICFP’2000, (2000) - - \bibitem {SmallCheck} - C. Runciman, M. Naylor, F. Lindblad. \emph{SmallCheck and Lazy SmallCheck: automatic exhaustive testing for small values}, in Haskell Symposium ’08. pp. 37–48. ACM (2008) - - \bibitem {BlueCheck} - M. Naylor and S. W. Moore. \emph{A Generic Synthesisable Test Bench}, in MEMOCODE 2015, pp. 128–137 (2015) - - \bibitem {Blarney} - \emph{Blarney}, https://github.com/mn416/blarney - -\end{thebibliography} - - -\newpage -\section*{Timetable and Milestones} - -\subsection*{25th October to 21st November} - -Research property-based testing for software and also hardware, making sure to -fully understand the related work. Setup and test the SmallCheck/QuickCheck -libraries for Haskell, to better understand how they work and to improve skills -with Haskell. -Learn to use Blarney, building some example circuits as a learning exercise. - -Milestones: Small Blarney modules of combinatorial logic implemented. Structure of testing framework and type-based generators designed. - - -\subsection*{22nd November to 5th December} - -Setup BlueCheck and Bluespec to test synthesizing test benches to an -FPGA. -Decide with the help of Matt on final design of the testing library, with -further literature study if necessary. Create the enumerative generators. - -Milestones: Structure necessary to meet the success criteria laid out and -ready to work on my own over the Christmas vacation. - -\subsection*{6th to 26th December (Christmas vacation)} - -Complete success criteria, namely: Implement a Haskell library for automatic -testing of combinatorial circuits written in Blarney. If any problems arise -can use second half of Christmas vacation to finish the work, at the cost of -fewer additional features. Otherwise if finished early start work on -Dissertation. - -Milestones: Code satisfies the first point of the success criteria. Introduction -chapter of Dissertation mostly complete. - -\subsection*{27th December to 16th January (Christmas vacation)} - -Start building additional features as able, with priority for synthesizing test -benches to an FPGA. Write Preparation chapter of Dissertation and start work on -Implementation chapter. - -Milestones: Synthesized test bench runs on FPGA. First 2 chapters of Dissertation -mostly complete and structure of Implementation chapter laid out. Some of the -proposed additional features complete. - -\subsection*{17th January to 27th February} - -Create progress report and presentation. -Run the library on the example buggy circuits in preparation for Evaluation -chapter. Start of lent term is very intense so use the long time at low intensity -to make small improvements and find any bugs. - -Milestones: Progress report and presentation done. Test data for Evaluation -generated. - -\subsection*{28th February to 12th March} - -Complete all additional features and clean up code. Project should be stable -at this point, with all changes being only minor after this point. - -Milestones: Project is complete and stable to allow writing Dissertation. - -\subsection*{13th March to 23rd April (Easter vacation)} - -Finish up the Introduction and Preparation chapters and write Implementation -chapter. Make only small crucial changes to code (e.g. bug fixes) - -Milestones: First 3 chapters of Dissertation complete. Codebase finalized, -ready for submission. - -\subsection*{13th March to 23rd April (Easter vacation)} - -Write Evaluation and Conclusions chapters, running any additional tests to gather -evaluation data if necessary. I can use this time to do additional work on the -project if Timetable has been moved back, otherwise for revision for final exams. - -Milestones: Dissertation finished, ready for submission if necessary. - -\subsection*{24th April to 7th May} - -Review whole project, check the Dissertation, and spend a final few -days on whatever is in greatest need of attention. - -Milestones: Dissertation is polished. Submission of Dissertation. - -\newpage -\section*{Resources Required} - -\begin{description} - -\item [Haskell:] ghc version 8.6.1 required for Blarney, but the default -apt get ghc installs version 8.0.2 (this is what is on MCS) so must be -downloaded manually. - -\item [CL account:] can be used to access required version of ghc if necessary, also to -use Bluespec/BlueCheck if necessary. Resource sponsor is \textbf{Simon Moore (swm11)} - -\item [Blarney:] downloaded with git clone. - -\item [FPGA:] for synthesizing testing benches. Resource sponsor is \textbf{Simon Moore (swm11)} - -\item [Machines in College:] similar to MCS machines, only needed if personal -hardware fails. - -\item [Personal laptop and computer:]- - -\begin{description} - -\item [My laptop:] 2.30 GHz CPU, 8 GB RAM, 118 GB Solid-state disk for OS -and 447 GB Solid-state disk for data, Windows OS with Ubuntu VM - -\item [My computer:] 3.50 GHz CPU, 16 GB RAM, 256 GB Solid-state disk for OS -and 1 TB Hard disk for data, Windows OS with Ubuntu VM - -\item [Contingency plans:] My contingency plans against data loss are that everything -will be held under git on GitHub with daily checkpoints to -my Google Drive and also weekly to USB Flash Drive kept only for -that purpose. -My contingency plans against hardware/software failure are -that I can easily transition my work to the MCS/CL machines - -\end{description} - -\end{description} - - - -\end{document} \ No newline at end of file diff --git a/proposal/3a_cover_sheet.pdf b/proposal/3a_cover_sheet.pdf deleted file mode 100644 index 2b4b36c..0000000 Binary files a/proposal/3a_cover_sheet.pdf and /dev/null differ diff --git a/proposal/DRAFT1_Part_II_Project_Proposal.pdf b/proposal/DRAFT1_Part_II_Project_Proposal.pdf deleted file mode 100644 index 66ee363..0000000 Binary files a/proposal/DRAFT1_Part_II_Project_Proposal.pdf and /dev/null differ diff --git a/proposal/FINAL_Part_II_Project_Proposal.pdf b/proposal/FINAL_Part_II_Project_Proposal.pdf deleted file mode 100644 index bb8abc1..0000000 Binary files a/proposal/FINAL_Part_II_Project_Proposal.pdf and /dev/null differ diff --git a/work/.vscode/settings.json b/work/.vscode/settings.json deleted file mode 100644 index 44b5910..0000000 --- a/work/.vscode/settings.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "ghcSimple.feature.rangeType": false -} \ No newline at end of file diff --git a/work/.vscode/tasks.json b/work/.vscode/tasks.json deleted file mode 100644 index befd970..0000000 --- a/work/.vscode/tasks.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - // See https://go.microsoft.com/fwlink/?LinkId=733558 - // for the documentation about the tasks.json format - "version": "2.0.0", - "tasks": [ - { - "label": "Run Blarney", - "type": "shell", - "command": "../Temp/SimulateBlarney.sh ${file}", - "group": { - "kind": "build", - "isDefault": true - } - } - ] -} \ No newline at end of file diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_04_36.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_04_36.txt deleted file mode 100644 index 6aa5996..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_04_36.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m37.691s -user 1m37.619s -sys 0m0.016s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_14_10.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_14_10.txt deleted file mode 100644 index 9bab735..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_14_10.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.493s -user 1m25.359s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_23_22.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_23_22.txt deleted file mode 100644 index 59ae299..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_23_22.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.458s -user 1m25.340s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_32_34.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_32_34.txt deleted file mode 100644 index 3b0d302..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_32_34.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.433s -user 1m25.431s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_41_46.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_41_46.txt deleted file mode 100644 index 0c9ff55..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_41_46.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.451s -user 1m25.453s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_50_59.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_50_59.txt deleted file mode 100644 index b5f5d21..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_00_50_59.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.397s -user 1m25.268s -sys 0m0.012s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_00_11.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_00_11.txt deleted file mode 100644 index 1933a6d..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_00_11.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.519s -user 1m25.469s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_09_22.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_09_22.txt deleted file mode 100644 index 310f03e..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_09_22.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.455s -user 1m25.444s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_18_34.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_18_34.txt deleted file mode 100644 index fd8b272..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_18_34.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.344s -user 1m25.339s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_27_46.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_27_46.txt deleted file mode 100644 index d8e366a..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_27_46.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.357s -user 1m25.358s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_36_57.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_36_57.txt deleted file mode 100644 index c4229bc..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_36_57.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.320s -user 1m25.313s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_46_08.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_46_08.txt deleted file mode 100644 index 94a7442..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_46_08.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.532s -user 1m25.530s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_55_19.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_55_19.txt deleted file mode 100644 index 76eb386..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_01_55_19.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.297s -user 1m25.287s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_04_31.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_04_31.txt deleted file mode 100644 index 137192a..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_04_31.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.531s -user 1m25.530s -sys 0m0.001s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_13_42.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_13_42.txt deleted file mode 100644 index 418d4ce..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_13_42.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.410s -user 1m25.405s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_22_53.txt b/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_22_53.txt deleted file mode 100644 index 9eba325..0000000 --- a/work/BuggySuite/Results/Evaluation/ActoraStack/output_2020_01_05_02_22_53.txt +++ /dev/null @@ -1,9 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 136 - -- All tests passed to depth 2 at time 14008 - -- All tests passed to depth 3 at time 1253240 - -=== All tests passed to maximum specified depth of 4 at time 106587960 === - -real 1m25.338s -user 1m25.334s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_06_15.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_06_15.txt deleted file mode 100644 index 0db55aa..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_06_15.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m47.582s -user 1m47.446s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_15_37.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_15_37.txt deleted file mode 100644 index b1bac6a..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_15_37.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.975s -user 1m45.945s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_24_49.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_24_49.txt deleted file mode 100644 index 88ae63d..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_24_49.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m46.448s -user 1m46.452s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_34_01.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_34_01.txt deleted file mode 100644 index 16ce2be..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_34_01.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m46.014s -user 1m46.002s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_43_13.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_43_13.txt deleted file mode 100644 index 6b6720b..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_43_13.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m47.561s -user 1m47.560s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_52_26.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_52_26.txt deleted file mode 100644 index 34b6995..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_00_52_26.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.919s -user 1m45.847s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_01_38.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_01_38.txt deleted file mode 100644 index 2f65b55..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_01_38.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m46.095s -user 1m46.095s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_10_49.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_10_49.txt deleted file mode 100644 index 4ffc22e..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_10_49.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m46.024s -user 1m45.972s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_20_00.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_20_00.txt deleted file mode 100644 index 4ad2bd5..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_20_00.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m47.557s -user 1m47.557s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_29_13.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_29_13.txt deleted file mode 100644 index 6a48eaf..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_29_13.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m46.089s -user 1m46.089s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_38_24.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_38_24.txt deleted file mode 100644 index c91e33e..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_38_24.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.880s -user 1m45.833s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_47_35.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_47_35.txt deleted file mode 100644 index f536328..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_47_35.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.933s -user 1m45.930s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_56_46.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_56_46.txt deleted file mode 100644 index cb1489d..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_01_56_46.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.895s -user 1m45.767s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_05_58.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_05_58.txt deleted file mode 100644 index b8ec70c..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_05_58.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.892s -user 1m45.803s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_15_09.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_15_09.txt deleted file mode 100644 index 2d253e8..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_15_09.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.982s -user 1m45.845s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_24_20.txt b/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_24_20.txt deleted file mode 100644 index 8ea0dc5..0000000 --- a/work/BuggySuite/Results/Evaluation/BRAMStack/output_2020_01_05_02_24_20.txt +++ /dev/null @@ -1,16 +0,0 @@ -- All tests passed to depth 0 at time 0 - -- All tests passed to depth 1 at time 66 - -- All tests passed to depth 2 at time 3333 - -- All tests passed to depth 3 at time 142725 - -- All tests passed to depth 4 at time 5892645 - -=== Found failing case at depth 5 after 233373867 ticks: TopEq {01 v 00} === -0: Push 0x01 -1: Push 0x00 -2: Push 0x00 -3: Pop -4: Pop -5: 'TopEq {01 v 00}' fails - -real 1m45.914s -user 1m45.914s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_08_11.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_08_11.txt deleted file mode 100644 index ad071b0..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_08_11.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.456s -user 0m0.456s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_17_25.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_17_25.txt deleted file mode 100644 index 2ff3a79..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_17_25.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.460s -user 0m0.459s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_26_37.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_26_37.txt deleted file mode 100644 index e2391f9..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_26_37.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.459s -user 0m0.459s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_35_49.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_35_49.txt deleted file mode 100644 index df294c1..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_35_49.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.454s -user 0m0.450s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_45_02.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_45_02.txt deleted file mode 100644 index a09e155..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_45_02.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.460s -user 0m0.454s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_54_14.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_54_14.txt deleted file mode 100644 index 78171ba..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_00_54_14.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.455s -user 0m0.456s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_03_25.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_03_25.txt deleted file mode 100644 index 7665bfb..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_03_25.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.454s -user 0m0.455s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_12_37.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_12_37.txt deleted file mode 100644 index 7665bfb..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_12_37.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.454s -user 0m0.455s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_21_50.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_21_50.txt deleted file mode 100644 index d745139..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_21_50.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.461s -user 0m0.460s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_31_01.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_31_01.txt deleted file mode 100644 index 1bc7cf8..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_31_01.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.459s -user 0m0.455s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_40_12.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_40_12.txt deleted file mode 100644 index ad071b0..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_40_12.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.456s -user 0m0.456s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_49_23.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_49_23.txt deleted file mode 100644 index 1ee8110..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_49_23.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.456s -user 0m0.455s -sys 0m0.001s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_58_34.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_58_34.txt deleted file mode 100644 index e8e771e..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_01_58_34.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.458s -user 0m0.459s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_07_45.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_07_45.txt deleted file mode 100644 index e1243f0..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_07_45.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.462s -user 0m0.458s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_16_57.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_16_57.txt deleted file mode 100644 index 78171ba..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_16_57.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.455s -user 0m0.456s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_26_08.txt b/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_26_08.txt deleted file mode 100644 index 0f1670b..0000000 --- a/work/BuggySuite/Results/Evaluation/CPU/output_2020_01_05_02_26_08.txt +++ /dev/null @@ -1,6 +0,0 @@ -- All tests passed to depth 0 at time 0 - -=== All tests passed to maximum specified depth of 1 at time 803008 === - -real 0m0.455s -user 0m0.455s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_08_13.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_08_13.txt deleted file mode 100644 index 7678c57..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_08_13.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.208s -user 1m31.219s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_17_27.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_17_27.txt deleted file mode 100644 index 478818e..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_17_27.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.223s -user 1m31.202s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_26_39.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_26_39.txt deleted file mode 100644 index bf34e6e..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_26_39.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.231s -user 1m31.226s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_35_51.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_35_51.txt deleted file mode 100644 index 69aaf56..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_35_51.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.146s -user 1m31.146s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_45_04.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_45_04.txt deleted file mode 100644 index ffe0bd8..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_45_04.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.154s -user 1m31.129s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_54_16.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_54_16.txt deleted file mode 100644 index e58dd4a..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_00_54_16.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.117s -user 1m31.014s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_03_27.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_03_27.txt deleted file mode 100644 index 77b5956..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_03_27.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.079s -user 1m31.034s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_12_39.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_12_39.txt deleted file mode 100644 index 422f807..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_12_39.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.047s -user 1m31.048s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_21_51.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_21_51.txt deleted file mode 100644 index eaf1038..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_21_51.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.069s -user 1m31.020s -sys 0m0.017s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_31_03.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_31_03.txt deleted file mode 100644 index d21bb12..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_31_03.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.045s -user 1m31.045s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_40_14.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_40_14.txt deleted file mode 100644 index b94d258..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_40_14.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m30.998s -user 1m30.902s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_49_25.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_49_25.txt deleted file mode 100644 index 93ad61f..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_49_25.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.000s -user 1m30.876s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_58_36.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_58_36.txt deleted file mode 100644 index f2f41d3..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_01_58_36.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.129s -user 1m31.123s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_07_47.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_07_47.txt deleted file mode 100644 index ed94a4d..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_07_47.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m31.299s -user 1m31.295s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_16_59.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_16_59.txt deleted file mode 100644 index cba572f..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_16_59.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m30.975s -user 1m30.945s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_26_10.txt b/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_26_10.txt deleted file mode 100644 index 089d51b..0000000 --- a/work/BuggySuite/Results/Evaluation/FirstHot/output_2020_01_05_02_26_10.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m30.968s -user 1m30.830s -sys 0m0.020s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_02_25.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_02_25.txt deleted file mode 100644 index 3437eaf..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_02_25.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.585s -user 1m46.580s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_04_15.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_04_15.txt deleted file mode 100644 index 56a2d6e..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_04_15.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.462s -user 1m46.461s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_06_04.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_06_04.txt deleted file mode 100644 index 9c8a797..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_06_04.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.917s -user 1m46.916s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_07_54.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_07_54.txt deleted file mode 100644 index 14d8a8c..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_07_54.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.417s -user 1m46.359s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_09_43.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_09_43.txt deleted file mode 100644 index fa97e8e..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_09_43.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m47.644s -user 1m47.644s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_11_34.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_11_34.txt deleted file mode 100644 index 2c67d9f..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_11_34.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.468s -user 1m46.467s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_13_24.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_13_24.txt deleted file mode 100644 index ea3b49b..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_13_24.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.387s -user 1m46.324s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_15_13.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_15_13.txt deleted file mode 100644 index b172753..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_15_13.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.594s -user 1m46.593s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_17_03.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_17_03.txt deleted file mode 100644 index 53ed03b..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_17_03.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.450s -user 1m46.450s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_18_52.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_18_52.txt deleted file mode 100644 index ba38829..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_18_52.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.411s -user 1m46.357s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_20_41.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_20_41.txt deleted file mode 100644 index 8a65f3a..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_20_41.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.463s -user 1m46.400s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_22_31.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_22_31.txt deleted file mode 100644 index e1f9382..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_22_31.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.682s -user 1m46.676s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_24_20.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_24_20.txt deleted file mode 100644 index e507cbc..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_24_20.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.503s -user 1m46.503s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_26_10.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_26_10.txt deleted file mode 100644 index 766a558..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_26_10.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.383s -user 1m46.330s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_27_59.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_27_59.txt deleted file mode 100644 index 0a5f37a..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_27_59.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.479s -user 1m46.479s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_29_49.txt b/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_29_49.txt deleted file mode 100644 index 30436c4..0000000 --- a/work/BuggySuite/Results/Evaluation/Sorter/output_2020_14_05_22_29_49.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 134217727-- - -real 1m46.473s -user 1m46.472s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_11_43.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_11_43.txt deleted file mode 100644 index 9a3a870..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_11_43.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.999s -user 1m17.869s -sys 0m0.012s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_20_56.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_20_56.txt deleted file mode 100644 index 225a761..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_20_56.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m18.084s -user 1m18.106s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_30_08.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_30_08.txt deleted file mode 100644 index ccf732e..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_30_08.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m18.024s -user 1m18.022s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_39_20.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_39_20.txt deleted file mode 100644 index a32525e..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_39_20.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.900s -user 1m17.901s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_48_33.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_48_33.txt deleted file mode 100644 index c0fce39..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_48_33.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.843s -user 1m17.843s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_57_44.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_57_44.txt deleted file mode 100644 index f335c5c..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_00_57_44.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.944s -user 1m17.943s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_06_56.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_06_56.txt deleted file mode 100644 index f8b180a..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_06_56.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.841s -user 1m17.798s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_16_07.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_16_07.txt deleted file mode 100644 index 91654ae..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_16_07.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.822s -user 1m17.823s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_25_20.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_25_20.txt deleted file mode 100644 index 120f8dd..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_25_20.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.752s -user 1m17.631s -sys 0m0.016s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_34_31.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_34_31.txt deleted file mode 100644 index ace812c..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_34_31.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.846s -user 1m17.841s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_43_42.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_43_42.txt deleted file mode 100644 index f89eba7..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_43_42.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.847s -user 1m17.845s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_52_53.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_52_53.txt deleted file mode 100644 index 27aa0d5..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_01_52_53.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.824s -user 1m17.818s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_02_04.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_02_04.txt deleted file mode 100644 index 23e9ed0..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_02_04.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.872s -user 1m17.871s -sys 0m0.001s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_11_16.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_11_16.txt deleted file mode 100644 index e43ecc3..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_11_16.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m18.289s -user 1m18.273s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_20_27.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_20_27.txt deleted file mode 100644 index ac2bce4..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_20_27.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.836s -user 1m17.831s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_29_38.txt b/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_29_38.txt deleted file mode 100644 index 2c7dc5b..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums/output_2020_01_05_02_29_38.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 1073741823-- - -real 1m17.924s -user 1m17.881s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_13_03.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_13_03.txt deleted file mode 100644 index 841e060..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_13_03.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.261s -user 1m5.222s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_22_15.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_22_15.txt deleted file mode 100644 index f7167dd..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_22_15.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.202s -user 1m5.194s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_31_27.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_31_27.txt deleted file mode 100644 index ed6427b..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_31_27.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.228s -user 1m5.222s -sys 0m0.005s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_40_39.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_40_39.txt deleted file mode 100644 index 893a0cc..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_40_39.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.179s -user 1m5.180s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_49_52.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_49_52.txt deleted file mode 100644 index bff3591..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_49_52.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.277s -user 1m5.180s -sys 0m0.012s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_59_04.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_59_04.txt deleted file mode 100644 index c5fa80e..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_00_59_04.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.241s -user 1m5.240s -sys 0m0.001s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_08_15.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_08_15.txt deleted file mode 100644 index c722dd5..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_08_15.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.150s -user 1m5.064s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_17_27.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_17_27.txt deleted file mode 100644 index ee34139..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_17_27.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.165s -user 1m5.111s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_26_39.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_26_39.txt deleted file mode 100644 index 162e431..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_26_39.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.143s -user 1m5.143s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_35_50.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_35_50.txt deleted file mode 100644 index 6244c99..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_35_50.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.118s -user 1m5.117s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_45_01.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_45_01.txt deleted file mode 100644 index 270ee2c..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_45_01.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.201s -user 1m5.113s -sys 0m0.004s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_54_13.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_54_13.txt deleted file mode 100644 index 2652fc0..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_01_54_13.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.085s -user 1m5.070s -sys 0m0.008s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_03_24.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_03_24.txt deleted file mode 100644 index 1189632..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_03_24.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.111s -user 1m5.013s -sys 0m0.012s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_12_36.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_12_36.txt deleted file mode 100644 index db9baf5..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_12_36.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.082s -user 1m5.082s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_21_47.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_21_47.txt deleted file mode 100644 index e845e3c..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_21_47.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m5.133s -user 1m5.133s -sys 0m0.000s diff --git a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_30_57.txt b/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_30_57.txt deleted file mode 100644 index 40a4b35..0000000 --- a/work/BuggySuite/Results/Evaluation/Sums_Parallel/output_2020_01_05_02_30_57.txt +++ /dev/null @@ -1,5 +0,0 @@ ---All tests passed at time 536870911-- - -real 1m7.854s -user 1m7.854s -sys 0m0.000s diff --git a/work/Check1/Check_05-11-19.hs b/work/Check1/Check_05-11-19.hs deleted file mode 100644 index 81007ae..0000000 --- a/work/Check1/Check_05-11-19.hs +++ /dev/null @@ -1,46 +0,0 @@ --- First focus on the most simple properties: forall bitvectors of constant size something must hold. --- Initially an exercise of getting used to using blarney and haskell, so code quite clunky. --- Check returns a list of Actions that check each enumeration, want to incorporate this checking into the test function. --- Struggling with Haskell/Blarney monads --- Successfully tested on first hot example - -import Blarney -import Blarney.Recipe - -data Prop = Assert (Bit 1) | Forall (Bit 8 -> Prop) - -check :: Integer -> Prop -> [Action ()] -check depth prop = (checkGenerate "" depth 0 prop) - where - -- String is just for debugging, Integer tracks what case we are on - checkGenerate :: String -> Integer -> Integer -> Prop -> [Action ()] - checkGenerate s _ _ (Assert value) = [do - display "Test" s ", result: " (value) - ] - checkGenerate s maxDepth currDepth (Forall f) - | currDepth >= maxDepth = appliedForall - | otherwise = appliedForall ++ checkGenerate s maxDepth (currDepth+1) (Forall f) - where - appliedForall = checkGenerate (s ++ " " ++ show currDepth) maxDepth 0 (f (fromInteger currDepth)) - - -firstHot :: Bit 8 -> Bit 8 -firstHot x = x .&. ((inv x) .+. 1) - -top :: Module () -top = do - let prop_HotBitCommon = Forall \x -> Assert (x .&. (firstHot x) .==. (firstHot x)) - - let testSeq = Par (map Action (check (2^8-1) prop_HotBitCommon)) - done <- run (reg 1 0) testSeq - - globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - (when done finish) - - globalTime <== globalTime.val + 1 - display "Time: " (globalTime.val) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check1/Check_05-11-19_Clean.hs b/work/Check1/Check_05-11-19_Clean.hs deleted file mode 100644 index e65217a..0000000 --- a/work/Check1/Check_05-11-19_Clean.hs +++ /dev/null @@ -1,37 +0,0 @@ --- First focus on the most simple properties: forall bitvectors of constant size something must hold. --- Initially an exercise of getting used to using blarney and haskell, so code quite clunky. --- Check returns a list of Actions that check each enumeration, want to incorporate this checking into the test function. --- Struggling with Haskell/Blarney monads --- Successfully tested on first hot example - -import Blarney -import Blarney.Recipe - -data Prop = Assert (Bit 1) | Forall (Bit 8 -> Prop) - -check :: Integer -> Prop -> [Action ()] -check depth prop = (checkGenerate "" depth 0 prop) - where - checkGenerate :: String -> Integer -> Integer -> Prop -> [Action ()] - checkGenerate s _ _ (Assert value) = [display "Test" s ", result: " (value)] - checkGenerate s maxDepth currDepth (Forall f) - | currDepth >= maxDepth = appliedForall - | otherwise = appliedForall ++ checkGenerate s maxDepth (currDepth+1) (Forall f) - where - appliedForall = checkGenerate (s ++ " " ++ show currDepth) maxDepth 0 (f (fromInteger currDepth)) - - -firstHot :: Bit 8 -> Bit 8 -firstHot x = x .&. ((inv x) .+. 1) - -top :: Module () -top = do - let prop_HotBitCommon = Forall \x -> Assert (x .&. (firstHot x) .==. (firstHot x)) - - let testSeq = Par (map Action (check (2^8-1) prop_HotBitCommon)) - done <- run (reg 1 0) testSeq - always do - (when done finish) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check1/Check_Minimal.hs b/work/Check1/Check_Minimal.hs deleted file mode 100644 index b36c223..0000000 --- a/work/Check1/Check_Minimal.hs +++ /dev/null @@ -1,33 +0,0 @@ -import Blarney - -type Property = (String, Prop) -data Prop = Assert (Bit 1) | Forall (Bit 8 -> Prop) - -check :: Integer -> Property -> Module () -check depth (name, property) = always do - pass <- (checkGenerate 0 name property 1) - when pass (display "P") >> finish - where - checkGenerate _ fName (Assert val) disp = do - when (val.inv .&. disp) (display "F: " fName) - return (val .&. disp) - checkGenerate currVal fName prop@(Forall f) disp = do - let appName = (fName ++ " " ++ show currVal) - passed <- checkGenerate 0 appName (f $ fromInteger currVal) disp - if (currVal >= depth) then return passed else - checkGenerate (currVal+1) fName prop passed - - - -firstHot :: Bit 8 -> Bit 8 -firstHot x = x .&. (x.inv .+. 1) - -top :: Module () -top = do - --let prop_HotBitCommon = ("HotBitCommon", Forall \x -> Assert (x .&. (firstHot x) .==. (firstHot x))) - --check (2^3-1) prop_HotBitCommon - let prop_SubComm = Forall \x -> Forall \y -> Assert (x.-.y .==. y.-.x) - check (2^6-1) ("SubCommutativity", prop_SubComm) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check1/Check_Minimal_2.hs b/work/Check1/Check_Minimal_2.hs deleted file mode 100644 index e469487..0000000 --- a/work/Check1/Check_Minimal_2.hs +++ /dev/null @@ -1,33 +0,0 @@ -import Blarney - -type Property = (String, Prop) -data Prop = Assert (Bit 1) | Forall (Bit 8 -> Prop) - -check :: Integer -> Property -> Module () -check depth (name, property) = always do - pass <- (checkGenerate name property 1) - when pass (display "P") >> finish - where - checkGenerate fName (Assert val) pass = do - when (val.inv .&. pass) (display "F: " fName) - return (val .&. pass) - checkGenerate fName (Forall f) pass = do - let appName = \x -> (fName ++ " " ++ show x) - feedForward [checkGenerate (appName x) (f $ constant x) | x <- [0 .. depth]] pass - feedForward [] pass = return pass - feedForward (tc:tcs) pass = tc pass >>= feedForward tcs - - - -firstHot :: Bit 8 -> Bit 8 -firstHot x = x .&. (x.inv .+. 1) - -top :: Module () -top = do - --let prop_HotBitCommon = ("HotBitCommon", Forall \x -> Assert (x .&. (firstHot x) .==. (firstHot x))) - --check (2^3-1) prop_HotBitCommon - let prop_SubComm = Forall \x -> Forall \y -> Assert (x.-.y .==. y.-.x) - check (2^6-1) ("SubCommutativity", prop_SubComm) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check2/Check_24-11.hs b/work/Check2/Check_24-11.hs deleted file mode 100644 index b234358..0000000 --- a/work/Check2/Check_24-11.hs +++ /dev/null @@ -1,86 +0,0 @@ --- Writing some nicer Haskell with list comprehension to generate list inputs. --- But we still have a fixed sized bitvector input, want to generalise to Bits class - am struggling with Haskell types, want to avoid using extensions --- Also want to separate input 'generation' from testing (also allows user to specify custom generators) --- Possibly sequential testing to allow for synthesis. --- Need for always passing around display action for the result is not nice. --- successfully test a sorter network - -import Blarney - -data Prop = Assert (Bit 1) | Forall (Bit 8 -> Prop) | ForallList Integer ([Bit 1] -> Prop) - -genListInputs :: Integer -> Integer -> [[Integer]] -genListInputs maxDepth currLength - | currLength <= 0 = [[]] - | otherwise = []:[ x:xs | x <- [0 .. maxDepth], xs <- (genListInputs maxDepth (currLength-1))] - -applyToProp :: (Prop, Action ()) -> [(Prop, Action ())] -applyToProp prop@(Assert _, _) = [prop] -applyToProp (prop@(Forall f), disp) = - [(f (unpack (constant x)), disp >> display_ x ", ") | x <- [0 .. 2^8-1]] -applyToProp (prop@(ForallList maxLength f), disp) = - [(f (map (\x -> (unpack (constant x))) xs), disp >> display_ (fshowList xs) ", ") | xs <- (genListInputs (2^1-1) maxLength)] - - - -genInputs :: [(Prop, Action ())] -> [(Prop, Action ())] -genInputs [] = [] -genInputs props@((Assert _, _):_) = props -genInputs props@((Forall _, _):_) = - genInputs (concatMap (applyToProp) props) -genInputs props@((ForallList _ _, _):_) = - genInputs (concatMap (applyToProp) props) - -displayProps :: [(Prop, Action ())] -> Action () -displayProps [] = finish -displayProps ((Assert p, disp):props) = do - _ <- display_ "Test with inputs: " - disp - _ <- display "\tresult: " (p) - displayProps props -displayProps _ = noAction - -checkTwo :: Prop -> Action () -checkTwo prop = do - let initial = [(prop, noAction)] - let checkCases = (genInputs initial) - displayProps checkCases - -check :: Prop -> Module() -check prop = do - let testSeq = (checkTwo prop) - always do - testSeq - - -twoSort :: KnownNat n => (Bit n, Bit n) -> (Bit n, Bit n) -twoSort (a :: Bit n, b) = let halfSize = constant (toInteger (valueOf @(n))) in - (b - a) + halfSize .>=. halfSize ? ((a, b), (b, a)) ---twoSort (a, b) = a .<. b ? ((a, b), (b, a)) - -bubble :: KnownNat n => [Bit n] -> [Bit n] -bubble [] = [] -bubble [x] = [x] -bubble (x:y:rest) = bubble (small:rest) ++ [big] - where (small, big) = twoSort (x, y) - -sort :: KnownNat n => [Bit n] -> [Bit n] -sort [] = [] -sort (x:xs) = smallest : sort rest - where (smallest:rest) = bubble (x:xs) - -isSorted :: KnownNat n => [Bit n] -> Bit 1 -isSorted [] = 1 -isSorted [_] = 1 -isSorted (x1:x2:xs) = (x1 .<=. x2) .&. isSorted (x2:xs) - - - -top :: Module () -top = do - let propSort = ForallList 4 \a -> Assert (isSorted (sort a)) - check propSort - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check3/Check_24-11.hs b/work/Check3/Check_24-11.hs deleted file mode 100644 index 7c1e67c..0000000 --- a/work/Check3/Check_24-11.hs +++ /dev/null @@ -1,122 +0,0 @@ --- Writing some nicer Haskell with list comprehension to generate list inputs. --- But we still have a fixed sized bitvector input, want to generalise to Bits class - am struggling with Haskell types, want to avoid using extensions --- Also want to separate input 'generation' from testing (also allows user to specify custom generators) --- Possibly sequential testing to allow for synthesis. --- Need for always passing around display action for the result is not nice. --- successfully test a sorter network - -import Blarney -import Check3.Generator - -data TestBench = TestBench - { runTest :: Action () - , increment :: Action (Bit 1) - } deriving (Generic, Interface) - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: Generator a => (a -> Prop) -> Prop - - -makeAssertTestBench :: (Bit 1) -> TestBench -makeAssertTestBench result = - TestBench { runTest = when (inv result) do - display "Failed the test." >> finish - , increment = return (constant 1) - } - -createIncrementAction :: Generator a => (TestBench, a, [Int]) -> Action (Bit 1) -createIncrementAction (tb, state) = - case (next state) of - ((NApply done inc):xs) -> do - if (done) then (reset state >> return tb.increment) - else (inc >> return (constant 0)) - [] -> return tb.increment - where createIncrementAction2 (tb, []) = return (tb.increment) - createIncrementAction2 (tb, ((NApply done inc):xs)) = if(done) then (reset state >> createIncrementAction2 (tb, xs) - else - - if (nexts) - then - if tb.isDone - then - noAction - else do - (register <== bitsGen.initial) - tb.increment - else - register <== (bitsGen.next $ register.val) - - -displayVarAndAbove :: SizedBits a => (String, Reg a) -> Action () -> Action () -displayVarAndAbove (name, register) dispAbove = do - dispAbove - display_ name "=" (pack (register.val)) ", " - - -{-Create the base TestBench here-} -checkGen :: (Prop, Action ()) -> Module (TestBench) -checkGen ((Assert p), dispValues) = do - return (makeAssertTestBench p dispValues) -checkGen ((Forall name f), dispValues) = do - inputs <- mapM makeReg [bitsGen.initial] - tbs <- mapM checkGen (map (\r -> (f (r.val), displayVarAndAbove (name, r) dispValues)) inputs) - let combined = zip tbs inputs - let isDoneComputed = andList $ (map (\myin -> bitsGen.isLast $ myin.val) inputs)++(extractDones tbs) - - return TestBench { runTest = runAllTbs tbs - , increment = if isDoneComputed then noAction else (doActionList (map createIncrementAction combined)) - , isDone = isDoneComputed - } - - -check :: Prop -> Module(Bit 1) -check prop = do - tb <- (checkGen (prop, noAction)) - - globalTime :: Reg (Bit 32) <- makeReg 0 - testComplete :: Reg (Bit 1) <- makeReg 0 - always do - globalTime <== globalTime.val + 1 - when (inv (testComplete.val)) do - testComplete <== tb.isDone - tb.increment - tb.runTest - --display "Time: " (globalTime.val) - when (tb.isDone) do - display "Test pass" - return (testComplete.val) - - - -twoSort :: KnownNat n => (Bit n, Bit n) -> (Bit n, Bit n) -twoSort (a :: Bit n, b) = let halfSize = constant (toInteger (valueOf @(n))) in - (b - a) + halfSize .>=. halfSize ? ((a, b), (b, a)) ---twoSort (a, b) = a .<. b ? ((a, b), (b, a)) - -bubble :: KnownNat n => [Bit n] -> [Bit n] -bubble [] = [] -bubble [x] = [x] -bubble (x:y:rest) = bubble (small:rest) ++ [big] - where (small, big) = twoSort (x, y) - -sort :: KnownNat n => [Bit n] -> [Bit n] -sort [] = [] -sort (x:xs) = smallest : sort rest - where (smallest:rest) = bubble (x:xs) - -isSorted :: KnownNat n => [Bit n] -> Bit 1 -isSorted [] = 1 -isSorted [_] = 1 -isSorted (x1:x2:xs) = (x1 .<=. x2) .&. isSorted (x2:xs) - - - -top :: Module () -top = do - let propSort = ForallList 4 \a -> Assert (isSorted (sort a)) - check propSort - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check3/Generator.hs b/work/Check3/Generator.hs deleted file mode 100644 index d0ed5f0..0000000 --- a/work/Check3/Generator.hs +++ /dev/null @@ -1,71 +0,0 @@ --- Problem is that we cannot test aribtrary data structures (eg. that the user has defined) --- Solution is to come up with a generator datatype which the user can specify for custom types and these can then be tested --- Two possiblilities of stateful vs stateless generator. - --- Do we need to support user defined data? --- Need some way to guarantee that 't' can be stored in a register(s?), how to do for lists? - -{-# LANGUAGE MultiParamTypeClasses #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE FunctionalDependencies #-} -{-# LANGUAGE BlockArguments #-} -{-# LANGUAGE DataKinds #-} -{-# LANGUAGE NoImplicitPrelude #-} -{-# LANGUAGE DeriveGeneric #-} -{-# LANGUAGE DeriveAnyClass #-} -{-# LANGUAGE ConstraintKinds #-} -{-# LANGUAGE UndecidableInstances #-} -{-# LANGUAGE AllowAmbiguousTypes #-} -{-# LANGUAGE GADTs #-} - -module Check3.Generator where - -import Blarney -import Blarney.Queue - -type SizedBits a = (Bits a, KnownNat (SizeOf a)) - - -data Next where - NApply :: (Bit 1) -> (Action ()) -> Next - NForall :: Generator a => (Bit 1) -> (a -> Next) -> Next - -class Generator a where - initial :: Int -> Module(a) - reset :: a -> Action () - next :: a -> [Next] - -instance (SizedBits a) => Generator (Reg a) where - initial = \_ -> makeReg (unpack (constant 0)) - reset = \state -> state <== (unpack (constant 0)) - next = \state -> [NApply (pack (state.val) .!=. ones) (state <== (unpack $ (pack (state.val)) .+. 1))] - -instance (Generator a) => Generator [a] where - initial = \size -> mapM (\_ -> initial size) [0 .. size] - reset = \state -> foldr (>>) noAction (map reset state) - next = \state -> concat (map next state) - -instance (SizedBits t) => Generator (Queue t) where - initial = \_ -> makeQueue - reset = \queue -> queue.reset - next = \queue -> [NForall (queue.notFull) \(x :: Reg t) -> NApply (constant 0) $ (queue.enq) (x.val), NApply (queue.notEmpty) (queue.deq)] - - -{- -data GeneratorState t = GeneratorState - { peek :: t - , isLast :: Bit 1 - , reset :: Action () - , consume :: Action () - } deriving (Generic, Interface) - - -bitGen :: Bits a => Module (GeneratorState a) -bitGen = do - - Generator { - peek = constant 0, - next = \prev -> prev .+. 1, - isLast = \value -> value .==. ones -} --} \ No newline at end of file diff --git a/work/Check4/Check_22-01.hs b/work/Check4/Check_22-01.hs deleted file mode 100644 index 3f7574f..0000000 --- a/work/Check4/Check_22-01.hs +++ /dev/null @@ -1,200 +0,0 @@ -{-# LANGUAGE GADTs #-} - -import Blarney -import Blarney.RAM -import Check4.Stack -import Check4.Generator - -data TestBench = TestBench - { runTest :: Action () - , increment :: Action () - , isDone :: Bit 1 - , reset :: Action () - } deriving (Generic, Interface) - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: Generator a => String -> (a -> Prop) -> Prop - WhenAction :: (Bit 1) -> Action() -> Prop - - -isAssertProp :: Prop -> Bool -isAssertProp (Assert _) = True -isAssertProp (WhenAction _ _) = False -isAssertProp (Forall _ f) = isAssertProp (f initial) - -splitProps :: [Prop] -> ([Prop], [Prop]) -splitProps [] = ([], []) -splitProps (prop:props) = if (isAssertProp prop) then (prop:assert, sideEffect) else (assert, prop:sideEffect) - where (assert, sideEffect) = splitProps props - - -makeAssertTestBench :: (Bit 1) -> Action() -> TestBench -makeAssertTestBench result dispSetValues = - TestBench { runTest = when (inv result) (dispSetValues >> display "Failed the test." >> finish) - , increment = noAction - , isDone = constant 1 - , reset = noAction - } - -combineTestBenches :: Module [TestBench] -> Module TestBench -combineTestBenches mtbs = do - tbs <- mtbs - return (combineTBs tbs) - where - combineTBs [] = error "No Assert Props given" - combineTBs [tb] = tb - combineTBs (tb:tbs) = - TestBench { runTest = (when (inv (tb.isDone)) (tb.runTest)) >> (when (inv (tb2.isDone)) (tb2.runTest)) - , increment = tb.increment >> tb2.increment - , isDone = tb.isDone .&. tb2.isDone - , reset = tb.reset >> tb2.reset - } - where tb2 = combineTBs tbs - - -displayVarAndAbove :: SizedBits a => (String, a) -> Action () -> Action () -displayVarAndAbove (name, genVal) dispAbove = dispAbove >> display_ name "=" (pack genVal) ", " - -createIncrementAction :: SizedBits a => (TestBench, Reg a) -> Action () -createIncrementAction (tb, register) = do - if (isFinal $ register.val) then do - if tb.isDone - then - noAction - else do - (register <== initial) - tb.increment - else do - register <== (next $ register.val) - - -{-Create the base TestBench here-} -checkGen :: Action () -> Prop -> Module (TestBench) -checkGen dispValues (Assert p) = do - return (makeAssertTestBench p dispValues) -checkGen dispValues (Forall name f) = do - gen <- makeReg initial - tb <- checkGen (displayVarAndAbove (name, gen.val) dispValues) (f (gen.val)) - return TestBench { runTest = tb.runTest - , increment = createIncrementAction (tb, gen) - , isDone = isFinal (gen.val) .&. tb.isDone - , reset = (gen <== initial) >> tb.reset - } -checkGen _ (WhenAction _ _) = error "When in Assert check" - -runSeProp :: Prop -> Action() -runSeProp (WhenAction guard effect) = when guard effect - -applyPropIndexed :: KnownNat n => Integer -> [Prop] -> Bit n -> Action () -applyPropIndexed _ [] _ = noAction -applyPropIndexed currVal [prop] idx = do - when (idx .==. (constant currVal)) (runSeProp prop) -applyPropIndexed currVal (prop:props) idx = do - when (idx .==. (constant currVal)) (runSeProp prop) - applyPropIndexed (currVal+1) props idx - - -check :: Action() -> [Prop] -> Integer -> Module(Bit 1) -check rst props depth = do - let (asserts, sideEffects) = splitProps props - tb <- combineTestBenches $ mapM (checkGen noAction) asserts - dfsChecked :: RAM (Bit 8) (Bit 5) <- makeRAM -- TODO: Replace 32 with something like Bit (log depth) Bit log(length sideEffects) - currDepth :: Reg (Bit 8) <- makeReg 0 - - globalTime :: Reg (Bit 32) <- makeReg 0 - runTests :: Reg (Bit 1) <- makeReg 1 - allDone :: Reg (Bit 1) <- makeReg 0 - loadedRam :: Reg (Bit 1) <- makeReg 0 - incrementDfs :: Reg (Bit 1) <- makeReg 0 - always do - if (runTests.val) then do - display "Run tests" (currDepth.val) - tb.runTest - tb.increment - runTests <== inv (tb.isDone) - when (tb.isDone) (tb.reset) - else do - display "Inc depth" (currDepth.val) - if (incrementDfs.val) then do - if (loadedRam.val) then do - if ((dfsChecked.out) + 1 .>=. (constant (toInteger (length sideEffects)))) then do - if (currDepth.val) .==. zero then do - allDone <== 1 - display $ "All tests passed to depth " ++ (show depth) - finish - else do - store dfsChecked (currDepth.val) 0 - loadedRam <== 0 - currDepth <== (currDepth.val) - 1 - else do - store dfsChecked (currDepth.val) ((dfsChecked.out) + 1) - loadedRam <== 0 - currDepth <== 0 - runTests <== 1 - incrementDfs <== 0 - else do - load dfsChecked (currDepth.val) - loadedRam <== 1 - else do - if (currDepth.val .>=. (constant depth)) then do - incrementDfs <== 1 - when (currDepth.val .!=. zero) (currDepth <== (currDepth.val) - 1) - rst - display "Resetting" (currDepth.val) - else do - if (loadedRam.val) then do - applyPropIndexed 0 sideEffects (dfsChecked.out) - currDepth <== (currDepth.val) + 1 - runTests <== 1 - loadedRam <== 0 - else do - load dfsChecked (currDepth.val) - loadedRam <== 1 - globalTime <== globalTime.val + 1 - --display "Time: " (globalTime.val) - --when (tb.isDone) do - --display "Test pass" - return (allDone.val) - - - -twoSort :: KnownNat n => (Bit n, Bit n) -> (Bit n, Bit n) -twoSort (a :: Bit n, b) = let halfSize = constant (toInteger (valueOf @(n))) in - (b - a) + halfSize .>=. halfSize ? ((a, b), (b, a)) ---twoSort (a, b) = a .<. b ? ((a, b), (b, a)) - -bubble :: KnownNat n => [Bit n] -> [Bit n] -bubble [] = [] -bubble [x] = [x] -bubble (x:y:rest) = bubble (small:rest) ++ [big] - where (small, big) = twoSort (x, y) - -sort :: KnownNat n => [Bit n] -> [Bit n] -sort [] = [] -sort (x:xs) = smallest : sort rest - where (smallest:rest) = bubble (x:xs) - -isSorted :: KnownNat n => [Bit n] -> Bit 1 -isSorted [] = 1 -isSorted [_] = 1 -isSorted (x1:x2:xs) = (x1 .<=. x2) .&. isSorted (x2:xs) - - - -top :: Module () -top = do - stack1 :: Stack 10 (Bit 4) <- makeStack - stack2 :: Stack 10 (Bit 4) <- makeStack - let stackPush = WhenAction (1) (display "Pushing" >> (stack1.push1) 0 >> (stack2.push1) 0) -- (stack1.overflow.inv) .&. (stack2.overflow.inv) - let stackPop = WhenAction (1) (display "Popping" >> (stack1.pop) 1 >> (stack2.pop) 1) -- (stack1.underflow.inv) .&. (stack2.underflow.inv) - let propSort = Assert (stack1.top1 .==. stack2.top1) - done <- check ((stack1.pop) (stack1.size) >> (stack2.pop) (stack2.size)) [propSort, stackPush, stackPop] 2 - --always do - --when done - --finish - return () - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/Check4/Generator.hs b/work/Check4/Generator.hs deleted file mode 100644 index d7b4367..0000000 --- a/work/Check4/Generator.hs +++ /dev/null @@ -1,35 +0,0 @@ --- Problem is that we cannot test aribtrary data structures (eg. that the user has defined) --- Solution is to come up with a generator datatype which the user can specify for custom types and these can then be tested --- Two possiblilities of stateful vs stateless generator. - --- Do we need to support user defined data? --- Need some way to guarantee that 't' can be stored in a register(s?), how to do for lists? - -{-# LANGUAGE MultiParamTypeClasses #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE FunctionalDependencies #-} -{-# LANGUAGE BlockArguments #-} -{-# LANGUAGE DataKinds #-} -{-# LANGUAGE NoImplicitPrelude #-} -{-# LANGUAGE DeriveGeneric #-} -{-# LANGUAGE DeriveAnyClass #-} -{-# LANGUAGE ConstraintKinds #-} -{-# LANGUAGE UndecidableInstances #-} -{-# LANGUAGE AllowAmbiguousTypes #-} -{-# LANGUAGE GADTs #-} - -module Check4.Generator where - -import Blarney - -type SizedBits a = (Bits a, KnownNat (SizeOf a)) - -class SizedBits a => Generator a where - initial :: a - next :: a -> a - isFinal :: a -> (Bit 1) - -instance (SizedBits a) => Generator a where - initial = unpack (constant 0) - next current = unpack $ (pack current) .+. 1 - isFinal current = (pack current) .==. ones \ No newline at end of file diff --git a/work/Check4/Stack.hs b/work/Check4/Stack.hs deleted file mode 100644 index 6dfd985..0000000 --- a/work/Check4/Stack.hs +++ /dev/null @@ -1,238 +0,0 @@ -module Check4.Stack where - --- This module implements a full-throughput dual-port stack. - -import Blarney -import Blarney.RAM -import Blarney.Recipe - --- Interface --- ========= - --- Stack of 2^n items of type a -data Stack n a = - Stack { - -- Can push one or two items per cycle: - -- (push1 happens after push2) - push1 :: a -> Action () - , push2 :: a -> Action () - -- Push nth item from top - -- (n can be negative to implement a slide) - , copy :: Bit n -> Action () - -- Pop any number of items - -- (can be called in parallel with push1) - , pop :: Bit n -> Action () - -- Size of the stack - , size :: Bit n - -- Top two stack values - , top1 :: a - , top2 :: a - -- Watch for stack underflow/overflow - , underflow :: Bit 1 - , overflow :: Bit 1 - } - --- Implementation --- ============== - -makeStack :: (Bits a, KnownNat n) => Module (Stack n a) -makeStack = do - -- True dual port RAM - (ram1, ram2) <- makeTrueDualRAM - - -- Top two elements stored in registers - reg1 :: Reg a <- makeReg dontCare - reg2 :: Reg a <- makeReg dontCare - - -- Pointer to top of stack - sp :: Reg (Bit n) <- makeReg 0 - - -- Pointer plus one - sp1 :: Reg (Bit n) <- makeReg 1 - - -- When these signals are high, the RAM holds the - -- top stack elements, not the registers - unlatched1 :: Reg (Bit 1) <- makeDReg 0 - unlatched2 :: Reg (Bit 1) <- makeDReg 0 - let topVal1 = unlatched1.val ? (ram1.out, reg1.val) - let topVal2 = unlatched2.val ? (ram2.out, reg2.val) - - -- Interface wires - push1Wire <- makeWire dontCare - push2Wire <- makeWire dontCare - copyWire <- makeWire dontCare - popWire <- makeWire 0 - let pushOrCopy = push1Wire.active .|. copyWire.active - - -- Watch for overflow/underflow - let inc = push2Wire.active ? (2, pushOrCopy ? (1, 0)) - let (underflowFlag, spAfterPop) = (sp.val) `checkedSub` (popWire.val) - let (overflowFlag, spNew) = spAfterPop `checkedAdd` inc - - always do - -- Update stack pointer - sp <== spNew - sp1 <== (sp1.val - popWire.val) + inc - - -- Common address for ram1 - let addr1 = sp1.val - copyWire.val - - -- Pushing and not popping - when (pushOrCopy .&. popWire.active.inv) do - if push1Wire.active - then reg1 <== push1Wire.val - else do - if copyWire.val .==. 0 - then reg1 <== topVal1 - else if copyWire.val .==. 1 - then reg1 <== topVal2 - else unlatched1 <== true - if push2Wire.active - then do - reg2 <== push2Wire.val - store ram1 addr1 topVal1 - else do - reg2 <== topVal1 - load ram1 addr1 - store ram2 (sp.val) topVal2 - - -- Popping and not pushing - when (popWire.active .&. push1Wire.active.inv) do - unlatched2 <== true - load ram2 (sp.val - popWire.val) - if popWire.val .==. 1 - then reg1 <== topVal2 - else unlatched1 <== true - load ram1 (sp1.val - popWire.val) - - -- Pushing and popping - when (push1Wire.active .&. popWire.active) do - reg1 <== push1Wire.val - reg2 <== topVal2 - when (popWire.val .!=. 1) do - unlatched2 <== true - load ram2 (sp1.val - popWire.val) - - -- Neither pushing, nor popping - when (pushOrCopy.inv .&. popWire.active.inv) do - reg1 <== topVal1 - reg2 <== topVal2 - - return $ - Stack { - push1 = \a -> push1Wire <== a - , push2 = \a -> push2Wire <== a - , copy = \n -> copyWire <== n - , pop = \n -> popWire <== n - , size = sp.val - , top1 = topVal1 - , top2 = topVal2 - , underflow = underflowFlag - , overflow = underflowFlag.inv .&. overflowFlag - } - - --- Add and check for overflow -checkedAdd :: Bit n -> Bit n -> (Bit 1, Bit n) -checkedAdd a b = split result - where - z :: Bit 1 = 0 - result = (z # a) .+. (z # b) - --- Subtract and check for underflow -checkedSub :: Bit n -> Bit n -> (Bit 1, Bit n) -checkedSub a b = split result - where - z :: Bit 1 = 0 - result = (z # a) .-. (z # b) - - --- Test bench --- ========== - -testBench :: Module () -testBench = do - -- Create 256-element stack - stk :: Stack 8 (Bit 8) <- makeStack - - -- Sample test sequence - let test = - Seq [ - -- [] - Action do - push2 stk 1 - push1 stk 2 - -- [1, 2] - , Action do push1 stk 3 - -- [1, 2, 3] - , Action do - push1 stk 4 - display (stk.top1) " " (stk.top2) - -- [1, 2, 3, 4] - , Action do - copy stk 3 - display (stk.top1) " " (stk.top2) - -- [1, 2, 3, 4, 1] - , Action do - pop stk 1 - display (stk.top1) " " (stk.top2) - -- [1, 2, 3, 4] - , Action do - display (stk.top1) " " (stk.top2) - -- [1, 2, 3, 4] - , Action do - display (stk.top1) " " (stk.top2) - push1 stk 10 - pop stk 1 - -- [1, 2, 3, 10] - , Action do - push1 stk 11 - display (stk.top1) " " (stk.top2) - -- [1, 2, 3, 10, 11] - , Action do - pop stk 3 - display (stk.top1) " " (stk.top2) - -- [1, 2] - , Action do - display (stk.top1) " " (stk.top2) - push2 stk 3 - push1 stk 4 - -- [1, 2, 3, 4] - , Action do - display (stk.top1) " " (stk.top2) - push2 stk 5 - push1 stk 6 - -- [1, 2, 3, 4, 5, 6] - , Action do - display (stk.top1) " " (stk.top2) - push2 stk 7 - push1 stk 8 - -- [1, 2, 3, 4, 5, 6, 7, 8] - , Action do - display (stk.top1) " " (stk.top2) - pop stk 6 - -- [1, 2] - , Action do - display (stk.top1) " " (stk.top2) - copy stk (-3) - -- [1, 2, 5] - , Action do - display (stk.top1) " " (stk.top2) - copy stk (-3) - -- [1, 2, 5, 6] - , Action do - display (stk.top1) " " (stk.top2) - ] - - runOnce test - --- Code generation --- =============== - -genTestBench :: IO () -genTestBench = - writeVerilogTop - testBench - "testBench" - "Stack-Verilog/" - diff --git a/work/Check5/Check_23-01.hs b/work/Check5/Check_23-01.hs deleted file mode 100644 index 5bc9997..0000000 --- a/work/Check5/Check_23-01.hs +++ /dev/null @@ -1,164 +0,0 @@ -{-# LANGUAGE GADTs #-} - -import Blarney -import Blarney.Recipe -import Check5.TestBench -import Check5.Property -import Check5.Stack - ---import Blarney.Queue - - -check :: Action() -> [Prop] -> Int -> Module(Bit 1) -check rst props depth = do - let (asserts, sideEffects) = splitProps props - pureTB <- combinePureProps asserts - impureTB <- makeImpureTestBench depth rst sideEffects - - globalTime :: Reg (Bit 32) <- makeReg 0 - pureTestsDone :: Reg (Bit 1) <- makeReg 0 - displayingFail :: Reg (Bit 1) <- makeReg 0 - allDone :: Reg (Bit 1) <- makeReg 0 - _ <- always do - if (displayingFail.val) then do - impureTB.displayFailImpure - when (impureTB.depthDone) finish - else do - if(impureTB.edgeDone.inv .|. pureTestsDone.val) then do - if (impureTB.depthDone) then do - _ <- display "--All tests passed to depth " (impureTB.currMaxDepth) "--" - if ((impureTB.currMaxDepth) .>=. (constant (toInteger depth))) then do - allDone <== 1 - finish - else do - impureTB.incMaxDepth - else do - impureTB.runEdge - pureTestsDone <== 0 - --display "-ImpureEdge" - else do - pureTB.increment - pureTestsDone <== pureTB.isDone - when (pureTB.isDone) (pureTB.reset) - when (pureTB.failed) do - pureTB.displayFailPure - displayingFail <== 1 - --display "+PureCheck" - - globalTime <== globalTime.val + 1 - --display "------TICK------" - --display "Time: " (globalTime.val) - --when (tb.isDone) do - --display "Test pass" - return (allDone.val) - - - -twoSort :: KnownNat n => (Bit n, Bit n) -> (Bit n, Bit n) ---twoSort (a :: Bit n, b) = let halfSize = constant (toInteger (valueOf @(n))) in --- (b - a) + halfSize .>=. halfSize ? ((a, b), (b, a)) -twoSort (a, b) = a .<. b ? ((a, b), (b, a)) - -bubble :: KnownNat n => [Bit n] -> [Bit n] -bubble [] = [] -bubble [x] = [x] -bubble (x:y:rest) = bubble (small:rest) ++ [big] - where (small, big) = twoSort (x, y) - -sort :: KnownNat n => [Bit n] -> [Bit n] -sort [] = [] -sort (x:xs) = smallest : sort rest - where (smallest:rest) = bubble (x:xs) - -isSorted :: KnownNat n => [Bit n] -> Bit 1 -isSorted [] = 1 -isSorted [_] = 1 -isSorted (x1:x2:xs) = (x1 .<=. x2) .&. isSorted (x2:xs) - - - -checkCheck :: Module () -checkCheck = do - - stackSpec :: Stack (Bit 3) <- makeStackSpec 10 - stack :: Stack (Bit 3) <- makeStack 10 - - let stackPush = Impure "Push" \x -> (1 :: Bit 1, (stackSpec.push) x >> (stack.push) x) - let stackPop = Impure "Pop" (stackSpec.isEmpty.inv .&. stack.isEmpty.inv, (stackSpec.pop) >> (stack.pop)) - --let stackPushPopNop = Impure "Pop" \x -> (stack.isEmpty.inv, (stack.push) x >> (stack.pop)) - - let propStackTopEq = Pure "StackTopEq" (stackSpec.isEmpty .|. (stackSpec.top .==. stack.top)) - - let rst = (stackSpec.clear) >> (stack.clear) - _ <- check rst [propStackTopEq, stackPush, stackPop] 6 - - {- - let propSorted = Pure "Sorted" (5 :: Int, \(xs :: [Bit 2]) -> isSorted (sort xs)) - - let rst = noAction - _ <- check rst [propSorted] 10 - -} - {- - stackSpec :: Stack (Bit 3) <- makeStackSpec 10 - stack :: Stack (Bit 3) <- makeStack 10 - - let stackPush = Impure "Push" \x -> (1 :: Bit 1, Seq [Action $ (stackSpec.push) x, Action $ (stack.push) x]) - let stackPop = Impure "Pop" (stackSpec.isEmpty.inv .&. stack.isEmpty.inv, (stackSpec.pop) >> (stack.pop)) - --let stackPushPopNop = Impure "Pop" \x -> (stack.isEmpty.inv, (stack.push) x >> (stack.pop)) - - let propStackTopEq = Pure "StackTopEq" (stackSpec.isEmpty .|. (stackSpec.top .==. stack.top)) - - let rst = (stackSpec.clear) >> (stack.clear) - _ <- check rst [propStackTopEq, stackPush, stackPop] 6 - -} - - --always do - --when done - --finish - - {- - --queueOfEdgesTaken :: Queue (Bit 16) <- makeSizedQueue 3 - recStart :: Reg (Bit 1) <- makeReg 0 - let recipe = - Seq [ - Action do - display "Rec 0" - , Action do - display "Rec 1" - , Action do - display "Rec 2" - ] - recipeEnd <- run (recStart.val) recipe - let test = - Seq [ - Action do - recStart <== 1 - , Action do - recStart <== 0 - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - display recipeEnd - , Action do - noAction - , Action do - finish - ] - runOnce test - -} - return () - - -main :: IO () -main = writeVerilogTop checkCheck "top" "Out-Verilog/" diff --git a/work/Check5/Generator.hs b/work/Check5/Generator.hs deleted file mode 100644 index a3e3df5..0000000 --- a/work/Check5/Generator.hs +++ /dev/null @@ -1,47 +0,0 @@ --- Problem is that we cannot test aribtrary data structures (eg. that the user has defined) --- Solution is to come up with a generator datatype which the user can specify for custom types and these can then be tested --- Two possiblilities of stateful vs stateless generator. - --- Do we need to support user defined data? --- Need some way to guarantee that 't' can be stored in a register(s?), how to do for lists? - -{-# LANGUAGE MultiParamTypeClasses #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE FunctionalDependencies #-} -{-# LANGUAGE BlockArguments #-} -{-# LANGUAGE DataKinds #-} -{-# LANGUAGE NoImplicitPrelude #-} -{-# LANGUAGE DeriveGeneric #-} -{-# LANGUAGE DeriveAnyClass #-} -{-# LANGUAGE ConstraintKinds #-} -{-# LANGUAGE UndecidableInstances #-} -{-# LANGUAGE AllowAmbiguousTypes #-} -{-# LANGUAGE GADTs #-} - -module Check5.Generator where - -import Blarney - -type SizedBits a = (Bits a, KnownNat (SizeOf a)) - -class SizedBits a => Generator a where - initial :: a - next :: a -> a - isFinal :: a -> (Bit 1) - -instance (SizedBits a) => Generator a where - initial = unpack (constant 0) - next current = unpack $ (pack current) .+. 1 - isFinal current = (pack current) .==. ones - - -doActionList :: [Action ()] -> Action() -doActionList as = foldr (>>) noAction as - -incrementGenList :: Generator a => [a] -> [a] -incrementGenList as = igl 1 as - where igl :: Generator a => Bit 1 -> [a] -> [a] - igl _ [] = [] - igl inc (x:xs) = - let incXs = igl (inc .&. isFinal x) xs - in (unpack $ mux inc (mux (isFinal x) (initial, pack (next x)), pack x)):incXs \ No newline at end of file diff --git a/work/Check5/ImpureProp.hs b/work/Check5/ImpureProp.hs deleted file mode 100644 index bac336d..0000000 --- a/work/Check5/ImpureProp.hs +++ /dev/null @@ -1,177 +0,0 @@ -{-# LANGUAGE GADTs #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE RankNTypes #-} - -module Check5.ImpureProp where - -import Blarney -import Blarney.Recipe -import Blarney.Queue -import Check5.Generator - -{-| - Created for WhenActions Props, used as the interface to increase the depth of the sequential search --} -data ImpureEdge = ImpureEdge - -- Used to traverse from one depth to another. - -- Must be called on all ImpureEdges, not just the one being executed, - -- as all use a Queue to track the inputs at the current depth and so all - -- need this Action to be called to proceed to the next depth - -- First Bit 1 sets if this action should be displayed - -- Second Bit 1 indicated if this edge should run it's impure Action - -- (should only be set on one IpureEdge at a time) - { increaseDepthExec :: Bit 1 -> Bit 1 -> Action() - , depthIncDone :: Bit 1 - - -- Used during Increment phase: Increment bit -> Reset bit -> IncAction - , increaseDepthInc :: Bit 1 -> Bit 1 -> Action() - , edgeExhaused :: Bit 1 - - -- Usually includes enqueueing one extra element in depth queue - , increaseMaxDepth :: Action () - } - --- Class of Impure Props -class ImpureProp a where - iPropToTB :: Int -> a -> Module(ImpureEdge) - -instance ImpureProp (Bit 1, Action()) where - iPropToTB _ (guardAct, impureAction) = - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when (exec .&. guardAct) impureAction - when (disp) (display "\t[Executed: " guardAct "]") - , depthIncDone = 1 - , increaseDepthInc = \_ -> \_ -> noAction - , edgeExhaused = 1 - , increaseMaxDepth = noAction - } -{- -instance ImpureProp (Bit 1, Recipe) where - iPropToTB _ (guardAct, impureRecipe) = do - executingEdge <- makeReg 0 - execEdge <- makeReg 0 - edgeDone <- run (execEdge.val) impureRecipe - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> \_ -> do - when (disp) (display "\t[Executed: " guardAct "]") - when (exec .&. guardAct .&. executingEdge.val.inv) do - display "Starting edge" - executingEdge <== 1 - execEdge <== 1 - when (executingEdge.val) do - when (edgeDone.inv) (display "Not ending edge") - when edgeDone (display "Ending edge") - executingEdge <== edgeDone.inv - execEdge <== 0 - , depthIncDone = edgeDone .|. (guardAct.inv) - , increaseDepthInc = \_ -> \_ -> noAction - , edgeExhaused = 1 - , increaseMaxDepth = noAction - } --} -instance (Generator a, ImpureProp b) => ImpureProp (Int, [a] -> b) where - iPropToTB maxDepth (listLen, f) = do - if (maxDepth == 0) then do - let appliedVal = replicate listLen initial - ie <- iPropToTB maxDepth (f appliedVal) - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when disp (display_ (map pack appliedVal) " ") - (ie.increaseDepthExec) disp exec - , depthIncDone = ie.depthIncDone - , increaseDepthInc = ie.increaseDepthInc - , edgeExhaused = ie.edgeExhaused - , increaseMaxDepth = ie.increaseMaxDepth - } - else do - currMaxDepthReg :: Reg (Bit 16) <- makeReg 0 - let useQueue = currMaxDepthReg.val .>. 1 - queueOfElementsAppliedAtDepths :: Bits a => [Queue a] <- mapM makeSizedQueue (replicate listLen maxDepth) - regOfEdgeTaken :: Bits a => [Reg a] <- mapM makeReg (replicate listLen initial) - let currVal = map (\(q, r) -> unpack (mux useQueue (pack $ q.first, pack $ r.val))) (zip queueOfElementsAppliedAtDepths regOfEdgeTaken) - - let cycleDeq = when useQueue (doActionList (map deq queueOfElementsAppliedAtDepths)) - let cycleEnq = \newVal -> do { - if useQueue then (doActionList (map (\(q, nV) -> (q.enq) nV) (zip queueOfElementsAppliedAtDepths newVal))) - else (doActionList (map (\(r, nV) -> r <== nV) (zip regOfEdgeTaken newVal))) - } - - let amFinal = andList $ map isFinal currVal - let cycleQueue = \inc -> \rst -> do { - cycleDeq - ; if (rst .|. (inc .&. amFinal)) then - cycleEnq (replicate listLen initial) - else - if inc then - cycleEnq (incrementGenList currVal) - else - cycleEnq currVal - } - ie <- iPropToTB maxDepth (f currVal) - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when disp (display_ (map pack currVal) " ") - (cycleQueue 0 0) - (ie.increaseDepthExec) disp exec - , depthIncDone = ie.depthIncDone - , increaseDepthInc = \inc -> \rst -> cycleQueue inc rst >> (ie.increaseDepthInc) (inc .&. amFinal) rst - , edgeExhaused = amFinal .&. ie.edgeExhaused - , increaseMaxDepth = do - currMaxDepthReg <== currMaxDepthReg.val + 1 - cycleEnq (replicate listLen initial) - ie.increaseMaxDepth - } - - -instance (Generator a, ImpureProp b) => ImpureProp (a -> b) where - iPropToTB maxDepth f = - if (maxDepth == 0) then do - let appliedVal = initial - ie <- iPropToTB maxDepth (f appliedVal) - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when disp (display_ (pack appliedVal) " ") - (ie.increaseDepthExec) disp exec - , depthIncDone = ie.depthIncDone - , increaseDepthInc = ie.increaseDepthInc - , edgeExhaused = ie.edgeExhaused - , increaseMaxDepth = ie.increaseMaxDepth - } - else do - currMaxDepthReg :: Reg (Bit 16) <- makeReg 0 - let useQueue = currMaxDepthReg.val .>. 1 - queueOfElementsAppliedAtDepths :: Bits a => Queue a <- makeSizedQueue maxDepth - regOfEdgeTaken <- makeReg initial - let currVal = unpack (mux useQueue (pack $ queueOfElementsAppliedAtDepths.first, pack $ regOfEdgeTaken.val)) - let cycleDeq = when useQueue (queueOfElementsAppliedAtDepths.deq) - let cycleEnq = \newVal -> do { - if useQueue then ((queueOfElementsAppliedAtDepths.enq) newVal) - else (regOfEdgeTaken <== newVal) - } - - let amFinal = isFinal currVal - let cycleQueue = \inc -> \rst -> do { - cycleDeq - ; if (rst .|. (inc .&. amFinal)) then - cycleEnq initial - else - if inc then - cycleEnq (next currVal) - else - cycleEnq currVal - } - ie <- iPropToTB maxDepth (f currVal) - return ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when disp (display_ (pack currVal) " ") - (cycleQueue 0 0) - (ie.increaseDepthExec) disp exec - , depthIncDone = ie.depthIncDone - , increaseDepthInc = \inc -> \rst -> cycleQueue inc rst >> (ie.increaseDepthInc) (inc .&. amFinal) rst - , edgeExhaused = amFinal .&. ie.edgeExhaused - , increaseMaxDepth = do - currMaxDepthReg <== currMaxDepthReg.val + 1 - cycleEnq initial - ie.increaseMaxDepth - } \ No newline at end of file diff --git a/work/Check5/Property.hs b/work/Check5/Property.hs deleted file mode 100644 index df17840..0000000 --- a/work/Check5/Property.hs +++ /dev/null @@ -1,257 +0,0 @@ -{-# LANGUAGE GADTs #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE RankNTypes #-} - -module Check5.Property where - -import Blarney -import Blarney.Queue -import Check5.TestBench -import Check5.PureProp -import Check5.ImpureProp - -{- -data Prop where - Assert :: String -> (Bit 1) -> Action() -> Prop - Forall :: Generator a => String -> (a -> Prop) -> Prop - WhenAction :: String -> (Bit 1) -> Action() -> Prop --} --- All props must either be Pure or Impure -data Prop where - Pure :: PureProp a => String -> a -> Prop - Impure :: ImpureProp a => String -> a -> Prop - -splitProps :: [Prop] -> ([Prop], [Prop]) -splitProps [] = ([], []) -splitProps ((prop@(Pure _ _)):props) = - let (assert, sideEffect) = splitProps props - in (prop:assert, sideEffect) -splitProps ((prop@(Impure _ _)):props) = - let (assert, sideEffect) = splitProps props - in (assert, prop:sideEffect) - - - - - - - -purePropToTB :: Prop -> Module PureTestBench -purePropToTB (Impure _ _) = error "Impure in pure props" -purePropToTB (Pure name prop) = do - tb <- pPropToTB prop - return PureTestBench { increment = tb.increment - , isDone = tb.isDone - , reset = tb.reset - , failed = tb.failed - , displayFailPure = when (tb.failed) (display_ "*** " name " ") >> (tb.displayFailPure) - } - -combinePureProps :: [Prop] -> Module PureTestBench -combinePureProps pureProps = do - combinePPs pureProps - where - combinePPs [] = error "No Assert Props given" - combinePPs [prop] = purePropToTB prop - combinePPs (prop:props) = do - tb <- purePropToTB prop - tbOthers <- combinePPs props - return PureTestBench { increment = tb.increment >> tbOthers.increment - , isDone = tb.isDone .&. tbOthers.isDone - , reset = tb.reset >> tbOthers.reset - , failed = tb.failed .|. tbOthers.failed - , displayFailPure = tb.displayFailPure >> tbOthers.displayFailPure - } - - - - - -propsToEdgesWithSelect :: KnownNat n => Int -> [Prop] -> Module(Bit n -> ImpureEdge) -propsToEdgesWithSelect maxDepth props = do - allEdges <- propsToEdges props - return (\idx -> - ImpureEdge { - increaseDepthExec = sel idx (map increaseDepthExec allEdges) - , depthIncDone = sel idx (map depthIncDone allEdges) - , increaseDepthInc = sel idx (map increaseDepthInc allEdges) - , edgeExhaused = sel idx (map edgeExhaused allEdges) - , increaseMaxDepth = sel idx (map increaseMaxDepth allEdges) - }) - where propsToEdges [] = return [] - propsToEdges ((Pure _ _):xs) = propsToEdges xs - propsToEdges ((Impure name prop):xs) = do - ie <- iPropToTB maxDepth prop - let edge = ImpureEdge { - increaseDepthExec = \disp -> \exec -> do - when disp (display_ name " ") - (ie.increaseDepthExec) disp exec - , depthIncDone = ie.depthIncDone - , increaseDepthInc = ie.increaseDepthInc - , edgeExhaused = ie.edgeExhaused - , increaseMaxDepth = ie.increaseMaxDepth - } - edges <- propsToEdges xs - return (edge:edges) - - - - -makeImpureTestBench :: Int -> Action() -> [Prop] -> Module(ImpureTestBench) -makeImpureTestBench maxDepth rst impureProps = do - if (maxDepth == 0 || length impureProps == 0) then - return ImpureTestBench { - runEdge = noAction - , edgeDone = 1 - , incMaxDepth = noAction - , depthDone = 1 - , currMaxDepth = constant (toInteger maxDepth) - , displayFailImpure = noAction - } - else do - let impureEdgesLenBit = (constant (toInteger (length impureProps))) - - currDepth <- makeReg 0 - depthTestedTo <- makeReg 0 - currMaxDepthReg <- makeReg 0 - let useQueue = currMaxDepthReg.val .>. 1 - - queueOfEdgesTaken :: Queue (Bit 16) <- makeSizedQueue maxDepth - regOfEdgeTaken :: Reg (Bit 16) <- makeReg 0 - let selectBits = mux useQueue (queueOfEdgesTaken.first, regOfEdgeTaken.val) - let cycleDeq = when useQueue (queueOfEdgesTaken.deq) - let cycleEnq = \newVal -> do { - if useQueue then ((queueOfEdgesTaken.enq) newVal) - else (regOfEdgeTaken <== newVal) - } - - edgesWithSelect <- propsToEdgesWithSelect maxDepth impureProps - let edges = edgesWithSelect selectBits - - - - -- 0 is execute phase, 1 is increment phase - phase :: Reg (Bit 1) <- makeReg 0 - - -- Set to 1 to run a round of Pure Prop testing before - -- continuing to runEdge - runPureTests :: Reg (Bit 1) <- makeReg 1 - -- In increment phase stop incrementing as soon as - -- we hit an edge that we can increment - amIncrementing :: Reg (Bit 1) <- makeReg 1 - - -- Set to 1 to indicate we have tested all at this max depth - currMaxDepthDone :: Reg (Bit 1) <- makeReg 1 - - -- Cycle depth to 0 before displaying failing sequence - displayFailingEdges :: Reg (Bit 1) <- makeReg 0 - startedDisplayFailingEdges :: Reg (Bit 1) <- makeReg 0 - - -- Is 1 when all at currDepth are tested (and should go back to testing the first prop) - let currDepthDone = selectBits + 1 .>=. impureEdgesLenBit - -- Is 1 when we have reached the curr max depth - let isAtFinalDepth = currDepth.val + 1 .>=. currMaxDepthReg.val - -- What is the last tested depth - let lastTestDepth = mux (currDepth.val .!=. 0) (currDepth.val, currMaxDepthReg.val) - return ImpureTestBench { - runEdge = do - if (currMaxDepthDone.val) then - noAction - else do - -- Check if currently running edge, then wait until done. - -- Or if am finished incrementing and waiting for depth increase - if (edges.depthIncDone.inv) then - (edges.increaseDepthExec) 0 0 - else do - -- If am at max depth then reset, otherwise increment - -- IMPORTANT: inc or exec phase will still run after this - if isAtFinalDepth then do - phase <== phase.val.inv - currDepth <== 0 - -- If switching to exec phase then reset state - if (phase.val) then do - rst - when (depthTestedTo.val .==. 0) (runPureTests <== 1) - --display("Reset") - -- If switching to increment phase, start inc & disable testing - else do - amIncrementing <== 1 - else - (currDepth <== (currDepth.val) + 1) - -- Always want to cycle depth, since we increased it above - cycleDeq - -- Split on increment and execute phase - if(phase.val) then do - runPureTests <== 0 - --display "*IncPhase" - -- If am still incrementing then increment edge if it isn't exhaused, otherwise reset it - (edges.increaseDepthInc) (edges.edgeExhaused.inv .&. amIncrementing.val) (edges.edgeExhaused .&. amIncrementing.val) - - -- Cases for incrementing my current edge counter: - -- When current edge is exhausted and am at the end of all edges, go back to 0 - if (amIncrementing.val .&. edges.edgeExhaused .&. currDepthDone) then - (cycleEnq 0) - -- When edge is exhausted but I can still go to next edge - else if (amIncrementing.val .&. edges.edgeExhaused) then - (cycleEnq $ selectBits + 1) - else - -- Edge is not exhausted so either got incremented or we aren't incrementing -> do nothing - (cycleEnq selectBits) - - -- Since currDepthDone isn't done we mustv'e incremented an edge, so don't increment at next depth - when (inv currDepthDone) (amIncrementing <== 0) - - -- If I've reached the current max depth, and incremented all of the edges here, but still want to increment then am done - when (amIncrementing.val .&. currDepthDone .&. isAtFinalDepth) (currMaxDepthDone <== 1) - else do - --display "^ExecPhase" (currDepth.val) - --(edges.displayEdge) 1 - -- Start Pure Tests when we are at an untested depth - when (currDepth.val .>=. depthTestedTo.val) (runPureTests <== 1) - (edges.increaseDepthExec) 0 1 - cycleEnq selectBits - , edgeDone = (runPureTests.val) .&. edges.depthIncDone - -- When all possibilities to current depth exhausted - -- depthDone = 1 & incMaxDepth must be called - , incMaxDepth = do - -- Enqueue to queues - edges.increaseMaxDepth - cycleEnq 0 - -- Initialise values - amIncrementing <== 0 - depthTestedTo <== currMaxDepthReg.val - currMaxDepthReg <== currMaxDepthReg.val + 1 - currMaxDepthDone <== 0 - , depthDone = currMaxDepthDone.val - -- Get the current max depth we are testing - , currMaxDepth = currMaxDepthReg.val - -- Display last executed sequence, keep running until depthDone - , displayFailImpure = do - -- If am finished displaying, skip - if (currMaxDepthDone.val) then - noAction - else do - if ((currDepth.val .>. depthTestedTo.val) .&. displayFailingEdges.val) then - currMaxDepthDone <== 1 - else do - if isAtFinalDepth then do - if(displayFailingEdges.val) then do - currMaxDepthDone <== 1 - else do - rst - displayFailingEdges <== 1 - currDepth <== 0 - - else - (currDepth <== (currDepth.val) + 1) - - when (startedDisplayFailingEdges.val.inv) do - startedDisplayFailingEdges <== 1 - display "Impure actions taken (%0d):" lastTestDepth - - -- Display failing edge if have reset back to depth 0 - (edges.increaseDepthExec) (displayFailingEdges.val) (displayFailingEdges.val) - -- Always cycle edges taken, and edges - cycleDeq - cycleEnq selectBits - } \ No newline at end of file diff --git a/work/Check5/PureProp.hs b/work/Check5/PureProp.hs deleted file mode 100644 index 0cdb557..0000000 --- a/work/Check5/PureProp.hs +++ /dev/null @@ -1,89 +0,0 @@ -{-# LANGUAGE GADTs #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE RankNTypes #-} - -module Check5.PureProp where - -import Blarney -import Check5.TestBench -import Check5.Generator - - - --- Class of Pure Props -class PureProp a where - pPropToTB :: a -> Module(PureTestBench) - -instance PureProp (Bit 1) where - pPropToTB result = - return PureTestBench { - increment = noAction - , isDone = 1 - , reset = noAction - , failed = inv result - , displayFailPure = when (inv result) (display "failed! ***") - } - -instance (Generator a, PureProp b) => PureProp (a -> b) where - pPropToTB f = do - gen <- makeReg initial - tb <- pPropToTB (f $ gen.val) - let incrementAction = do { - if (isFinal $ gen.val) then do - if tb.isDone - then - noAction - else do - (gen <== initial) - tb.increment - else do - gen <== (next $ gen.val) - } - return PureTestBench { - increment = incrementAction - , isDone = isFinal (gen.val) .&. tb.isDone - , reset = (gen <== initial) >> tb.reset - , failed = tb.failed - , displayFailPure = when (tb.failed) (display_ (pack $ gen.val) " ") >> (tb.displayFailPure) - } - -instance (Generator a, PureProp b) => PureProp (Int, [a] -> b) where - pPropToTB (listLen, f) = do - gens <- mapM makeReg (replicate listLen initial) - let vals = map val gens - let resetRegAction = doActionList (map (\(r, nV) -> r <== nV) (zip gens (replicate listLen initial))) - let incRegAction = doActionList (map (\(r, nV) -> r <== nV) (zip gens (incrementGenList vals))) - let amFinal = andList $ map isFinal vals - tb <- pPropToTB (f vals) - let incrementAction = do { - if (amFinal) then do - if tb.isDone - then - noAction - else do - resetRegAction - tb.increment - else do - incRegAction - } - return PureTestBench { - increment = incrementAction - , isDone = amFinal .&. tb.isDone - , reset = resetRegAction >> tb.reset - , failed = tb.failed - , displayFailPure = when (tb.failed) (display_ (map pack vals) " ") >> (tb.displayFailPure) - } -{- -instance (PureProp a) => PureProp [a] where - pPropToTB [] = error "Must specify at least one Pure Property to test!" - pPropToTB [x] = pPropToTB x - pPropToTB (x:xs) = do - tb <- pPropToTB x - tbOthers <- pPropToTB xs - return PureTestBench { increment = tb.increment >> tbOthers.increment - , isDone = tb.isDone .&. tbOthers.isDone - , reset = tb.reset >> tbOthers.reset - , failed = tb.failed .|. tbOthers.failed - , displayFailPure = tb.displayFailPure >> tbOthers.displayFailPure - } --} \ No newline at end of file diff --git a/work/Check5/Stack.hs b/work/Check5/Stack.hs deleted file mode 100644 index c5867a9..0000000 --- a/work/Check5/Stack.hs +++ /dev/null @@ -1,114 +0,0 @@ -module Check5.Stack where - --- Blarney imports -import Blarney -import Blarney.Queue -import Blarney.Recipe - --- Standard imports -import Data.Proxy - --- Stack interface -data Stack a = - Stack { - push :: a -> Action () - , pop :: Action () - , top :: a - , isEmpty :: Bit 1 - , clear :: Action () - } - --- Buggy stack implementation --- (Parallel push and pop not supported) -makeStack :: Bits a => Int -> Module (Stack a) -makeStack logSize = do - -- Lift size to type-level number - liftNat logSize $ \(_ :: Proxy n) -> do - - -- RAM, wide enough to hold entire stack - ram :: RAM (Bit n) a <- makeDualRAMForward 0 - - -- Stack pointer - sp :: Reg (Bit n) <- makeReg 0 - - -- Top stack element - topReg :: Reg a <- makeReg dontCare - - -- Speculative read address - speculateReg :: Reg (Bit n) <- makeReg 0 - speculateWire :: Wire (Bit n) <- makeWire (sp.val) - - -- Read top element from RAM - always do - load ram (speculateWire.active ? (speculateWire.val, speculateReg.val)) - when (speculateWire.active) do - speculateReg <== speculateWire.val - - return $ - Stack { - push = \a -> do - topReg <== a - store ram (sp.val) (topReg.val) - speculateWire <== sp.val - sp <== sp.val + 1 - , pop = do - topReg <== ram.out - speculateWire <== sp.val - 1 -- BUG: should be sp.val - 2 - sp <== sp.val - 1 - , top = topReg.val - , isEmpty = sp.val .==. 0 - , clear = sp <== 0 - } - --- Stack specification --- (Parallel push and pop not supported) -makeStackSpec :: Bits a => Int -> Module (Stack a) -makeStackSpec logSize = - -- Lift size to type-level number - liftNat logSize $ \(_ :: Proxy n) -> do - - -- List of register, big enough to hold stack elements - elems :: [Reg a] <- replicateM (2^logSize) (makeReg dontCare) - - -- Size of stack - size :: Reg (Bit n) <- makeReg 0 - - return $ - Stack { - push = \a -> do - elems.head <== a - zipWithM_ (<==) (tail elems) (map val elems) - size <== size.val + 1 - , pop = do - zipWithM_ (<==) elems (tail (map val elems)) - size <== size.val - 1 - , top = elems.head.val - , isEmpty = size.val .==. 0 - , clear = size <== 0 - } - --- Top-level module -testBench :: Module () -testBench = do - -- Create 256-element stack - stk :: Stack (Bit 8) <- makeStack 8 - - -- Sample test sequence - let test = - Seq [ - Action do - push stk 1 - , Action do - push stk 2 - , Action do - push stk 3 - , Action do - pop stk - , Action do - pop stk - , Action do - display (stk.top) - finish - ] - - runOnce test \ No newline at end of file diff --git a/work/Check5/TestBench.hs b/work/Check5/TestBench.hs deleted file mode 100644 index b6c1461..0000000 --- a/work/Check5/TestBench.hs +++ /dev/null @@ -1,60 +0,0 @@ -{-# LANGUAGE GADTs #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE RankNTypes #-} - -module Check5.TestBench where - -import Blarney -import Check5.Generator - - -data PureTestBench = PureTestBench - { increment :: Action () - , isDone :: Bit 1 - , reset :: Action () - , failed :: Bit 1 - , displayFailPure :: Action () - } deriving (Generic, Interface) - - -data ImpureTestBench = ImpureTestBench - -- Traverse one edge, until edgeDone is 1 - { runEdge :: Action () - , edgeDone :: Bit 1 - -- When all possibilities to current depth exhausted - -- depthDone = 1 & incMaxDepth must be called - , incMaxDepth :: Action () - , depthDone :: Bit 1 - -- Get the current max depth we are testing - , currMaxDepth :: Bit 16 - -- Display last executed sequence, keep running until depthDone - , displayFailImpure :: Action () - } deriving (Generic, Interface) - - - --- Given a Bit number (idx) selecting an element of [a] only select ([a])[idx] -class Selectable a where - sel :: KnownNat n => Bit n -> [a] -> a - --- Always execute all actions, relevant Bits should already be selected -instance Selectable (Action ()) where - sel _ actions = runAll actions - where runAll [] = noAction - runAll [a] = a - runAll (a:as) = a >> (runAll as) - --- Only return true if selected bit is true -instance Selectable (Bit 1) where - sel idx elems = selIdx elems 0 - where selIdx [] _ = 0 - selIdx (e:es) currIdx = (e .&. (idx .==. (constant currIdx))) .|. selIdx es (currIdx + 1) - --- Only apply true if the given bitVal is true and also only to elem[idx] -instance Selectable b => Selectable (Bit 1 -> b) where - sel idx elems = \bitVal -> sel idx (applyIdx elems 0 bitVal) - where applyIdx [] _ _ = [] - applyIdx (e:es) currIdx bitVal = do - let appliedElem = e $ bitVal .&. (idx .==. (constant currIdx)) - let appliedAll = applyIdx es (currIdx + 1) bitVal - appliedElem:appliedAll \ No newline at end of file diff --git a/work/CheckFPGA_ActoraStack/Makefile b/work/CheckFPGA_ActoraStack/Makefile deleted file mode 100644 index 5539011..0000000 --- a/work/CheckFPGA_ActoraStack/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - "../../Temp/copy_bram_files.sh" & - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_ActoraStack/Src/Makefile b/work/CheckFPGA_ActoraStack/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_ActoraStack/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_ActoraStack/report.ods b/work/CheckFPGA_ActoraStack/report.ods deleted file mode 100644 index 3272d14..0000000 Binary files a/work/CheckFPGA_ActoraStack/report.ods and /dev/null differ diff --git a/work/CheckFPGA_ActoraStack/report_fmax.ods b/work/CheckFPGA_ActoraStack/report_fmax.ods deleted file mode 100644 index d596d9c..0000000 Binary files a/work/CheckFPGA_ActoraStack/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_ActoraStack/report_util.ods b/work/CheckFPGA_ActoraStack/report_util.ods deleted file mode 100644 index 220b199..0000000 Binary files a/work/CheckFPGA_ActoraStack/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_BRAMStack/BlarneyComponent.v b/work/CheckFPGA_BRAMStack/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_BRAMStack/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_BRAMStack/Blarney_hw.tcl b/work/CheckFPGA_BRAMStack/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_BRAMStack/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_BRAMStack/BlockRAM.v b/work/CheckFPGA_BRAMStack/BlockRAM.v deleted file mode 100644 index 87e79a7..0000000 --- a/work/CheckFPGA_BRAMStack/BlockRAM.v +++ /dev/null @@ -1,40 +0,0 @@ -// Single-port block RAM -// ===================== - -module BlockRAM ( - CLK, // Clock - DI, // Data in - ADDR, // Read address - WE, // Write enable - DO // Data out - ); - - parameter ADDR_WIDTH = 1; - parameter DATA_WIDTH = 1; - parameter INIT_FILE = "UNUSED"; - - input CLK; - input [DATA_WIDTH-1:0] DI; - input [ADDR_WIDTH-1:0] ADDR; - input WE; - output reg [DATA_WIDTH-1:0] DO; - reg [DATA_WIDTH-1:0] RAM[2**ADDR_WIDTH-1:0]; - - generate - if (INIT_FILE != "UNUSED") begin - initial $readmemh(INIT_FILE, RAM); - end - endgenerate - - always @(posedge CLK) - begin - if (WE) begin - RAM[ADDR] <= DI; - DO <= {DATA_WIDTH{1'hx}}; - end - else begin - DO <= RAM[ADDR]; - end - end - -endmodule diff --git a/work/CheckFPGA_BRAMStack/BlockRAMTrueDual.v b/work/CheckFPGA_BRAMStack/BlockRAMTrueDual.v deleted file mode 100644 index 4141941..0000000 --- a/work/CheckFPGA_BRAMStack/BlockRAMTrueDual.v +++ /dev/null @@ -1,54 +0,0 @@ -// True dual-port block RAM -// ======================== - -module BlockRAMTrueDual ( - CLK, // Clock - DI_A, // Data in - ADDR_A, // Read address - WE_A, // Write enable - DO_A, // Data out - DI_B, // Data in - ADDR_B, // Read address - WE_B, // Write enable - DO_B // Data out - ); - - parameter ADDR_WIDTH = 1; - parameter DATA_WIDTH = 1; - parameter INIT_FILE = "UNUSED"; - - input [(DATA_WIDTH-1):0] DI_A, DI_B; - input [(ADDR_WIDTH-1):0] ADDR_A, ADDR_B; - input WE_A, WE_B, CLK; - output reg [(DATA_WIDTH-1):0] DO_A, DO_B; - reg [DATA_WIDTH-1:0] RAM[2**ADDR_WIDTH-1:0]; - - generate - if (INIT_FILE != "UNUSED") begin - initial $readmemh(INIT_FILE, RAM); - end - endgenerate - - // Port A - always @(posedge CLK) - begin - if (WE_A) begin - RAM[ADDR_A] <= DI_A; - DO_A <= {DATA_WIDTH{1'hx}};; - end else begin - DO_A <= (WE_B && ADDR_A == ADDR_B) ? {DATA_WIDTH{1'hx}} : RAM[ADDR_A]; - end - end - - // Port B - always @(posedge CLK) - begin - if (WE_B) begin - RAM[ADDR_B] <= DI_B; - DO_B <= {DATA_WIDTH{1'hx}}; - end else begin - DO_B <= (WE_A && ADDR_A == ADDR_B) ? {DATA_WIDTH{1'hx}} : RAM[ADDR_B]; - end - end - -endmodule diff --git a/work/CheckFPGA_BRAMStack/JTAGUART.v b/work/CheckFPGA_BRAMStack/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_BRAMStack/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_BRAMStack/Makefile b/work/CheckFPGA_BRAMStack/Makefile deleted file mode 100644 index 5539011..0000000 --- a/work/CheckFPGA_BRAMStack/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - "../../Temp/copy_bram_files.sh" & - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_BRAMStack/SoC.qsys b/work/CheckFPGA_BRAMStack/SoC.qsys deleted file mode 100644 index d194ad5..0000000 --- a/work/CheckFPGA_BRAMStack/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_BRAMStack/SoCKitTop.qpf b/work/CheckFPGA_BRAMStack/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_BRAMStack/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_BRAMStack/SoCKitTop.qsf b/work/CheckFPGA_BRAMStack/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_BRAMStack/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_BRAMStack/SoCKitTop.sdc b/work/CheckFPGA_BRAMStack/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_BRAMStack/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_BRAMStack/SoCKitTop.v b/work/CheckFPGA_BRAMStack/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_BRAMStack/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_BRAMStack/Src/Makefile b/work/CheckFPGA_BRAMStack/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_BRAMStack/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_BRAMStack/report.ods b/work/CheckFPGA_BRAMStack/report.ods deleted file mode 100644 index 8f034f8..0000000 Binary files a/work/CheckFPGA_BRAMStack/report.ods and /dev/null differ diff --git a/work/CheckFPGA_BRAMStack/report_fmax.ods b/work/CheckFPGA_BRAMStack/report_fmax.ods deleted file mode 100644 index b20c095..0000000 Binary files a/work/CheckFPGA_BRAMStack/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_BRAMStack/report_util.ods b/work/CheckFPGA_BRAMStack/report_util.ods deleted file mode 100644 index 5b641a5..0000000 Binary files a/work/CheckFPGA_BRAMStack/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_CPU/BlarneyComponent.v b/work/CheckFPGA_CPU/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_CPU/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_CPU/Blarney_hw.tcl b/work/CheckFPGA_CPU/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_CPU/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_CPU/BlockRAM.v b/work/CheckFPGA_CPU/BlockRAM.v deleted file mode 100644 index 87e79a7..0000000 --- a/work/CheckFPGA_CPU/BlockRAM.v +++ /dev/null @@ -1,40 +0,0 @@ -// Single-port block RAM -// ===================== - -module BlockRAM ( - CLK, // Clock - DI, // Data in - ADDR, // Read address - WE, // Write enable - DO // Data out - ); - - parameter ADDR_WIDTH = 1; - parameter DATA_WIDTH = 1; - parameter INIT_FILE = "UNUSED"; - - input CLK; - input [DATA_WIDTH-1:0] DI; - input [ADDR_WIDTH-1:0] ADDR; - input WE; - output reg [DATA_WIDTH-1:0] DO; - reg [DATA_WIDTH-1:0] RAM[2**ADDR_WIDTH-1:0]; - - generate - if (INIT_FILE != "UNUSED") begin - initial $readmemh(INIT_FILE, RAM); - end - endgenerate - - always @(posedge CLK) - begin - if (WE) begin - RAM[ADDR] <= DI; - DO <= {DATA_WIDTH{1'hx}}; - end - else begin - DO <= RAM[ADDR]; - end - end - -endmodule diff --git a/work/CheckFPGA_CPU/BlockRAMTrueDual.v b/work/CheckFPGA_CPU/BlockRAMTrueDual.v deleted file mode 100644 index 4141941..0000000 --- a/work/CheckFPGA_CPU/BlockRAMTrueDual.v +++ /dev/null @@ -1,54 +0,0 @@ -// True dual-port block RAM -// ======================== - -module BlockRAMTrueDual ( - CLK, // Clock - DI_A, // Data in - ADDR_A, // Read address - WE_A, // Write enable - DO_A, // Data out - DI_B, // Data in - ADDR_B, // Read address - WE_B, // Write enable - DO_B // Data out - ); - - parameter ADDR_WIDTH = 1; - parameter DATA_WIDTH = 1; - parameter INIT_FILE = "UNUSED"; - - input [(DATA_WIDTH-1):0] DI_A, DI_B; - input [(ADDR_WIDTH-1):0] ADDR_A, ADDR_B; - input WE_A, WE_B, CLK; - output reg [(DATA_WIDTH-1):0] DO_A, DO_B; - reg [DATA_WIDTH-1:0] RAM[2**ADDR_WIDTH-1:0]; - - generate - if (INIT_FILE != "UNUSED") begin - initial $readmemh(INIT_FILE, RAM); - end - endgenerate - - // Port A - always @(posedge CLK) - begin - if (WE_A) begin - RAM[ADDR_A] <= DI_A; - DO_A <= {DATA_WIDTH{1'hx}};; - end else begin - DO_A <= (WE_B && ADDR_A == ADDR_B) ? {DATA_WIDTH{1'hx}} : RAM[ADDR_A]; - end - end - - // Port B - always @(posedge CLK) - begin - if (WE_B) begin - RAM[ADDR_B] <= DI_B; - DO_B <= {DATA_WIDTH{1'hx}}; - end else begin - DO_B <= (WE_A && ADDR_A == ADDR_B) ? {DATA_WIDTH{1'hx}} : RAM[ADDR_B]; - end - end - -endmodule diff --git a/work/CheckFPGA_CPU/JTAGUART.v b/work/CheckFPGA_CPU/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_CPU/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_CPU/SoC.qsys b/work/CheckFPGA_CPU/SoC.qsys deleted file mode 100644 index 28bf610..0000000 --- a/work/CheckFPGA_CPU/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_CPU/SoCKitTop.qpf b/work/CheckFPGA_CPU/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_CPU/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_CPU/SoCKitTop.qsf b/work/CheckFPGA_CPU/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_CPU/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_CPU/SoCKitTop.sdc b/work/CheckFPGA_CPU/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_CPU/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_CPU/SoCKitTop.v b/work/CheckFPGA_CPU/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_CPU/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_CPU/Src/Makefile b/work/CheckFPGA_CPU/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_CPU/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_CPU/report.ods b/work/CheckFPGA_CPU/report.ods deleted file mode 100644 index acf6270..0000000 Binary files a/work/CheckFPGA_CPU/report.ods and /dev/null differ diff --git a/work/CheckFPGA_CPU/report_fmax.ods b/work/CheckFPGA_CPU/report_fmax.ods deleted file mode 100644 index 9463a89..0000000 Binary files a/work/CheckFPGA_CPU/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_CPU/report_util.ods b/work/CheckFPGA_CPU/report_util.ods deleted file mode 100644 index 7aa0dd9..0000000 Binary files a/work/CheckFPGA_CPU/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_FirstHot/BlarneyComponent.v b/work/CheckFPGA_FirstHot/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_FirstHot/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_FirstHot/Blarney_hw.tcl b/work/CheckFPGA_FirstHot/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_FirstHot/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_FirstHot/JTAGUART.v b/work/CheckFPGA_FirstHot/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_FirstHot/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_FirstHot/Makefile b/work/CheckFPGA_FirstHot/Makefile deleted file mode 100644 index 0545ad7..0000000 --- a/work/CheckFPGA_FirstHot/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_FirstHot/SoC.qsys b/work/CheckFPGA_FirstHot/SoC.qsys deleted file mode 100644 index 0df5869..0000000 --- a/work/CheckFPGA_FirstHot/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_FirstHot/SoCKitTop.qpf b/work/CheckFPGA_FirstHot/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_FirstHot/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_FirstHot/SoCKitTop.qsf b/work/CheckFPGA_FirstHot/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_FirstHot/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_FirstHot/SoCKitTop.sdc b/work/CheckFPGA_FirstHot/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_FirstHot/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_FirstHot/SoCKitTop.v b/work/CheckFPGA_FirstHot/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_FirstHot/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_FirstHot/Src/Makefile b/work/CheckFPGA_FirstHot/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_FirstHot/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_FirstHot/report.ods b/work/CheckFPGA_FirstHot/report.ods deleted file mode 100644 index 5ca684c..0000000 Binary files a/work/CheckFPGA_FirstHot/report.ods and /dev/null differ diff --git a/work/CheckFPGA_FirstHot/report_fmax.ods b/work/CheckFPGA_FirstHot/report_fmax.ods deleted file mode 100644 index d877032..0000000 Binary files a/work/CheckFPGA_FirstHot/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_FirstHot/report_util.ods b/work/CheckFPGA_FirstHot/report_util.ods deleted file mode 100644 index 04c4017..0000000 Binary files a/work/CheckFPGA_FirstHot/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_Sorter/BlarneyComponent.v b/work/CheckFPGA_Sorter/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_Sorter/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_Sorter/Blarney_hw.tcl b/work/CheckFPGA_Sorter/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_Sorter/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_Sorter/JTAGUART.v b/work/CheckFPGA_Sorter/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_Sorter/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_Sorter/Makefile b/work/CheckFPGA_Sorter/Makefile deleted file mode 100644 index 0545ad7..0000000 --- a/work/CheckFPGA_Sorter/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_Sorter/SoC.qsys b/work/CheckFPGA_Sorter/SoC.qsys deleted file mode 100644 index 6371533..0000000 --- a/work/CheckFPGA_Sorter/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_Sorter/SoCKitTop.qpf b/work/CheckFPGA_Sorter/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_Sorter/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_Sorter/SoCKitTop.qsf b/work/CheckFPGA_Sorter/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_Sorter/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_Sorter/SoCKitTop.sdc b/work/CheckFPGA_Sorter/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_Sorter/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_Sorter/SoCKitTop.v b/work/CheckFPGA_Sorter/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_Sorter/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_Sorter/Src/Makefile b/work/CheckFPGA_Sorter/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_Sorter/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_Sorter/report.ods b/work/CheckFPGA_Sorter/report.ods deleted file mode 100644 index a44ad0b..0000000 Binary files a/work/CheckFPGA_Sorter/report.ods and /dev/null differ diff --git a/work/CheckFPGA_Sorter/report_fmax.ods b/work/CheckFPGA_Sorter/report_fmax.ods deleted file mode 100644 index 5448070..0000000 Binary files a/work/CheckFPGA_Sorter/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_Sorter/report_util.ods b/work/CheckFPGA_Sorter/report_util.ods deleted file mode 100644 index 56452b0..0000000 Binary files a/work/CheckFPGA_Sorter/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums/BlarneyComponent.v b/work/CheckFPGA_Sums/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_Sums/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_Sums/Blarney_hw.tcl b/work/CheckFPGA_Sums/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_Sums/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_Sums/JTAGUART.v b/work/CheckFPGA_Sums/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_Sums/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_Sums/Makefile b/work/CheckFPGA_Sums/Makefile deleted file mode 100644 index 0545ad7..0000000 --- a/work/CheckFPGA_Sums/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_Sums/SoC.qsys b/work/CheckFPGA_Sums/SoC.qsys deleted file mode 100644 index 0667df1..0000000 --- a/work/CheckFPGA_Sums/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_Sums/SoCKitTop.qpf b/work/CheckFPGA_Sums/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_Sums/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_Sums/SoCKitTop.qsf b/work/CheckFPGA_Sums/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_Sums/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_Sums/SoCKitTop.sdc b/work/CheckFPGA_Sums/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_Sums/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_Sums/SoCKitTop.v b/work/CheckFPGA_Sums/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_Sums/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_Sums/SoC_NoPLL.qsys b/work/CheckFPGA_Sums/SoC_NoPLL.qsys deleted file mode 100644 index 83434fb..0000000 --- a/work/CheckFPGA_Sums/SoC_NoPLL.qsys +++ /dev/null @@ -1,144 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_Sums/SoC_PLL.qsys b/work/CheckFPGA_Sums/SoC_PLL.qsys deleted file mode 100644 index 1551764..0000000 --- a/work/CheckFPGA_Sums/SoC_PLL.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_Sums/Src/Makefile b/work/CheckFPGA_Sums/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_Sums/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_Sums/report.ods b/work/CheckFPGA_Sums/report.ods deleted file mode 100644 index f298043..0000000 Binary files a/work/CheckFPGA_Sums/report.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums/report_fmax.ods b/work/CheckFPGA_Sums/report_fmax.ods deleted file mode 100644 index 09ae218..0000000 Binary files a/work/CheckFPGA_Sums/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums/report_util.ods b/work/CheckFPGA_Sums/report_util.ods deleted file mode 100644 index 17ce035..0000000 Binary files a/work/CheckFPGA_Sums/report_util.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums_Parallel/BlarneyComponent.v b/work/CheckFPGA_Sums_Parallel/BlarneyComponent.v deleted file mode 100644 index 94ded29..0000000 --- a/work/CheckFPGA_Sums_Parallel/BlarneyComponent.v +++ /dev/null @@ -1,58 +0,0 @@ -module BlarneyComponent - ( input wire clock - , input wire reset - - // Avalon memory-mapped JTAG UART interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - ); - - // Input stream - wire in_canGet; - wire [7:0] in_getData; - wire in_get; - - // Output stream - wire out_canGet; - wire [7:0] out_getData; - wire out_get; - - JTAGUART uart - ( .clock(clock) - , .reset(reset) - - // Avalon memory-mapped interface - , .address(address) - , .writedata(writedata) - , .write(write) - , .read(read) - , .waitrequest(waitrequest) - , .readdata(readdata) - - // Input stream - , .in_canGet(in_canGet) - , .in_getData(in_getData) - , .in_get(in_get) - - // Output stream - , .out_canGet(out_canGet) - , .out_getData(out_getData) - , .out_get(out_get) - ); - - Top top - ( .clock(clock) - , .reset(reset) - , .in_canPeek(out_canGet) - , .in_peek(out_getData) - , .in_consume_en(out_get) - , .out_consume_en(in_get) - , .out_peek(in_getData) - , .out_canPeek(in_canGet) - ); - -endmodule diff --git a/work/CheckFPGA_Sums_Parallel/Blarney_hw.tcl b/work/CheckFPGA_Sums_Parallel/Blarney_hw.tcl deleted file mode 100644 index 0ba03a1..0000000 --- a/work/CheckFPGA_Sums_Parallel/Blarney_hw.tcl +++ /dev/null @@ -1,117 +0,0 @@ -# TCL File Generated by Component Editor 16.1 -# Sun Mar 31 10:22:48 BST 2019 -# DO NOT MODIFY - - -# -# BlarneyComponent "BlarneyComponent" v1.0 -# 2019.03.31.10:22:48 -# -# - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - - -# -# module BlarneyComponent -# -set_module_property DESCRIPTION "" -set_module_property NAME BlarneyComponent -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME BlarneyComponent -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL BlarneyComponent -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file BlarneyComponent.v VERILOG PATH BlarneyComponent.v TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset reset reset Input 1 - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clock clk Input 1 - - -# -# connection point avalon_master -# -add_interface avalon_master avalon start -set_interface_property avalon_master addressUnits SYMBOLS -set_interface_property avalon_master associatedClock clock -set_interface_property avalon_master associatedReset reset -set_interface_property avalon_master bitsPerSymbol 8 -set_interface_property avalon_master burstOnBurstBoundariesOnly false -set_interface_property avalon_master burstcountUnits WORDS -set_interface_property avalon_master doStreamReads false -set_interface_property avalon_master doStreamWrites false -set_interface_property avalon_master holdTime 0 -set_interface_property avalon_master linewrapBursts false -set_interface_property avalon_master maximumPendingReadTransactions 0 -set_interface_property avalon_master maximumPendingWriteTransactions 0 -set_interface_property avalon_master readLatency 0 -set_interface_property avalon_master readWaitTime 1 -set_interface_property avalon_master setupTime 0 -set_interface_property avalon_master timingUnits Cycles -set_interface_property avalon_master writeWaitTime 0 -set_interface_property avalon_master ENABLED true -set_interface_property avalon_master EXPORT_OF "" -set_interface_property avalon_master PORT_NAME_MAP "" -set_interface_property avalon_master CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master address address Output 3 -add_interface_port avalon_master writedata writedata Output 32 -add_interface_port avalon_master write write Output 1 -add_interface_port avalon_master read read Output 1 -add_interface_port avalon_master waitrequest waitrequest Input 1 -add_interface_port avalon_master readdata readdata Input 32 - diff --git a/work/CheckFPGA_Sums_Parallel/JTAGUART.v b/work/CheckFPGA_Sums_Parallel/JTAGUART.v deleted file mode 100644 index 8a34d03..0000000 --- a/work/CheckFPGA_Sums_Parallel/JTAGUART.v +++ /dev/null @@ -1,102 +0,0 @@ -// This module provides a streaming interface to -// Altera's memory-mapped JTAG UART component. - -// State of the core -`define JTAG_IDLE 0 // Do nothing -`define JTAG_READ_DATA 1 // Consume char from UART, if available -`define JTAG_READ_WSPACE 2 // Read UART's CSR to determine write space -`define JTAG_WRITE_DATA 3 // Write char to UART's data register - -module JTAGUART - ( input wire clock - , input wire reset - - // Avalon memory-mapped interface - , output wire [2:0] address - , output wire [31:0] writedata - , output wire write - , output wire read - , input wire waitrequest - , input wire [31:0] readdata - - // Input stream - , input wire in_canGet - , input wire [7:0] in_getData - , output wire in_get - - // Output stream - , output wire out_canGet - , output wire [7:0] out_getData - , input wire out_get - ); - - // Input queue - reg inQueueFull = 0; - reg [7:0] inQueueData; - - assign in_get = in_canGet && !inQueueFull; - - // Output queue - reg outQueueFull = 0; - reg [7:0] outQueueData; - - assign out_canGet = outQueueFull; - assign out_getData = outQueueData; - - // This register is used to toggle between reading and writing - reg toggle = 0; - - // Current state of state machine - reg [1:0] state = `JTAG_IDLE; - - // Avalon memory-mapped outputs - assign address = - (state == `JTAG_READ_DATA || state == `JTAG_WRITE_DATA) ? 0 : 4; - assign writedata = {24'h0, inQueueData}; - assign write = state == `JTAG_WRITE_DATA; - assign read = state == `JTAG_READ_DATA || state == `JTAG_READ_WSPACE; - - // State machine - always @(posedge clock) begin - if (reset) begin - state <= `JTAG_IDLE; - outQueueFull <= 0; - inQueueFull <= 0; - end else begin - if (in_canGet && !inQueueFull) begin - inQueueData <= in_getData; - inQueueFull <= 1; - end - - if (out_get && outQueueFull) outQueueFull <= 0; - - case (state) - `JTAG_IDLE: - begin - toggle <= !toggle; - if (inQueueFull && toggle) - state <= `JTAG_READ_WSPACE; - else if (!outQueueFull) - state <= `JTAG_READ_DATA; - end - `JTAG_READ_DATA: - if (!waitrequest) begin - if (readdata[15] == 1) begin - outQueueFull <= 1; - outQueueData <= readdata[7:0]; - end - state <= `JTAG_IDLE; - end - `JTAG_READ_WSPACE: - if (!waitrequest) - state <= readdata[31:16] > 0 ? `JTAG_WRITE_DATA : `JTAG_IDLE; - `JTAG_WRITE_DATA: - if (!waitrequest) begin - inQueueFull <= 0; - state <= `JTAG_IDLE; - end - endcase - end - end - -endmodule diff --git a/work/CheckFPGA_Sums_Parallel/Makefile b/work/CheckFPGA_Sums_Parallel/Makefile deleted file mode 100644 index 0545ad7..0000000 --- a/work/CheckFPGA_Sums_Parallel/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -ifndef QUARTUS_ROOTDIR - $(error Please set QUARTUS_ROOTDIR) -endif - -.PHONY: one -one: - make -C Src - qsys-generate -syn SoC.qsys - quartus_sh --flow compile SoCKitTop.qpf - -.PHONY: dse -dse: - make -C Src - qsys-generate -syn SoC.qsys - quartus_dse SoCKitTop.qpf \ - --num-seeds 15 \ - --launcher local \ - --num-concurrent 4 -.PHONY: report -report: - quartus_dse SoCKitTop.qpf --report utilization - quartus_dse SoCKitTop.qpf --report fmax_summary - -.PHONY: download-sof -download-sof: - quartus_pgm -m jtag -o "p;SoCKitTop.sof" - -.PHONY: update-mif -update-mif: - quartus_cdb --update_mif SoCKitTop.qpf - quartus_asm SoCKitTop.qpf - -.PHONY: clean -clean: clean-mif - rm -f *.rpt *.msg *.summary *.sld *.sopcinfo *.jdi c5_pin_model_dump.txt - rm -f *.pin *.done *.qws *.sof *.csv *.qws *.smsg *.qdf - rm -rf dse* db incremental_db SoC .qsys_edit reconfig_mif SoC .qsys-edit - -.PHONY: clean-mif -clean-mif: - rm -f *.mif - make -C Src clean diff --git a/work/CheckFPGA_Sums_Parallel/SoC.qsys b/work/CheckFPGA_Sums_Parallel/SoC.qsys deleted file mode 100644 index 3b96f51..0000000 --- a/work/CheckFPGA_Sums_Parallel/SoC.qsys +++ /dev/null @@ -1,370 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - diff --git a/work/CheckFPGA_Sums_Parallel/SoCKitTop.qpf b/work/CheckFPGA_Sums_Parallel/SoCKitTop.qpf deleted file mode 100644 index 66f583e..0000000 --- a/work/CheckFPGA_Sums_Parallel/SoCKitTop.qpf +++ /dev/null @@ -1,32 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -# Date created = 17:54:00 November 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "17:54:00 November 19, 2019" - -# Revisions - -PROJECT_REVISION = "SoCKitTop" -PROJECT_REVISION = "SocKitTop" diff --git a/work/CheckFPGA_Sums_Parallel/SoCKitTop.qsf b/work/CheckFPGA_Sums_Parallel/SoCKitTop.qsf deleted file mode 100644 index 19bf257..0000000 --- a/work/CheckFPGA_Sums_Parallel/SoCKitTop.qsf +++ /dev/null @@ -1,747 +0,0 @@ -#============================================================ -# Build by Terasic V1.0.0 -#============================================================ - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES -set_global_assignment -name TOP_LEVEL_ENTITY "SocKit_golden_top" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON JUL 1 14:21:10 2013" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA - - -#============================================================ -# AUD -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK - -#============================================================ -# DDR3 -#============================================================ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to DDR3_WE_n - -#============================================================ -# FAN -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL - -#============================================================ -# HPS -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_A[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_p -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_n[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_p[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_BK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_D_C -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LCM_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SW[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP - -#============================================================ -# HSMC -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_IN0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLK_OUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p[7] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[0] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[3] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[4] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[5] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[6] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p[7] -set_instance_assignment -name IO_STANDARD HCSL -to HSMC_REF_CLK_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_p[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_n[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_p[16] - -#============================================================ -# IRDA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] - -#============================================================ -# OSC -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A - -#============================================================ -# PCIE -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_PERST_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PCIE_WAKE_n - -#============================================================ -# RESET -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n - -#============================================================ -# SI5338 -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] - -#============================================================ -# TEMP -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK - -#============================================================ -# USB -#============================================================ -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_CLK -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_B2_DATA[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_EMPTY -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_FULL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_OE_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RD_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_RESET_n -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SCL -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_SDA -set_instance_assignment -name IO_STANDARD "1.5 V" -to USB_WR_n - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - - -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_location_assignment PIN_AC27 -to AUD_ADCDAT -set_location_assignment PIN_AG30 -to AUD_ADCLRCK -set_location_assignment PIN_AE7 -to AUD_BCLK -set_location_assignment PIN_AG3 -to AUD_DACDAT -set_location_assignment PIN_AH4 -to AUD_DACLRCK -set_location_assignment PIN_AH30 -to AUD_I2C_SCLK -set_location_assignment PIN_AF30 -to AUD_I2C_SDAT -set_location_assignment PIN_AD26 -to AUD_MUTE -set_location_assignment PIN_AC9 -to AUD_XCK -set_location_assignment PIN_AJ14 -to DDR3_A[0] -set_location_assignment PIN_AK14 -to DDR3_A[1] -set_location_assignment PIN_AH12 -to DDR3_A[2] -set_location_assignment PIN_AJ12 -to DDR3_A[3] -set_location_assignment PIN_AG15 -to DDR3_A[4] -set_location_assignment PIN_AH15 -to DDR3_A[5] -set_location_assignment PIN_AK12 -to DDR3_A[6] -set_location_assignment PIN_AK13 -to DDR3_A[7] -set_location_assignment PIN_AH13 -to DDR3_A[8] -set_location_assignment PIN_AH14 -to DDR3_A[9] -set_location_assignment PIN_AJ9 -to DDR3_A[10] -set_location_assignment PIN_AK9 -to DDR3_A[11] -set_location_assignment PIN_AK7 -to DDR3_A[12] -set_location_assignment PIN_AK8 -to DDR3_A[13] -set_location_assignment PIN_AG12 -to DDR3_A[14] -set_location_assignment PIN_AH10 -to DDR3_BA[0] -set_location_assignment PIN_AJ11 -to DDR3_BA[1] -set_location_assignment PIN_AK11 -to DDR3_BA[2] -set_location_assignment PIN_AH7 -to DDR3_CAS_n -set_location_assignment PIN_AJ21 -to DDR3_CKE -set_location_assignment PIN_AA15 -to DDR3_CK_n -set_location_assignment PIN_AA14 -to DDR3_CK_p -set_location_assignment PIN_AB15 -to DDR3_CS_n -set_location_assignment PIN_AH17 -to DDR3_DM[0] -set_location_assignment PIN_AG23 -to DDR3_DM[1] -set_location_assignment PIN_AK23 -to DDR3_DM[2] -set_location_assignment PIN_AJ27 -to DDR3_DM[3] -set_location_assignment PIN_AF18 -to DDR3_DQ[0] -set_location_assignment PIN_AE17 -to DDR3_DQ[1] -set_location_assignment PIN_AG16 -to DDR3_DQ[2] -set_location_assignment PIN_AF16 -to DDR3_DQ[3] -set_location_assignment PIN_AH20 -to DDR3_DQ[4] -set_location_assignment PIN_AG21 -to DDR3_DQ[5] -set_location_assignment PIN_AJ16 -to DDR3_DQ[6] -set_location_assignment PIN_AH18 -to DDR3_DQ[7] -set_location_assignment PIN_AK18 -to DDR3_DQ[8] -set_location_assignment PIN_AJ17 -to DDR3_DQ[9] -set_location_assignment PIN_AG18 -to DDR3_DQ[10] -set_location_assignment PIN_AK19 -to DDR3_DQ[11] -set_location_assignment PIN_AG20 -to DDR3_DQ[12] -set_location_assignment PIN_AF19 -to DDR3_DQ[13] -set_location_assignment PIN_AJ20 -to DDR3_DQ[14] -set_location_assignment PIN_AH24 -to DDR3_DQ[15] -set_location_assignment PIN_AE19 -to DDR3_DQ[16] -set_location_assignment PIN_AE18 -to DDR3_DQ[17] -set_location_assignment PIN_AG22 -to DDR3_DQ[18] -set_location_assignment PIN_AK22 -to DDR3_DQ[19] -set_location_assignment PIN_AF21 -to DDR3_DQ[20] -set_location_assignment PIN_AF20 -to DDR3_DQ[21] -set_location_assignment PIN_AH23 -to DDR3_DQ[22] -set_location_assignment PIN_AK24 -to DDR3_DQ[23] -set_location_assignment PIN_AF24 -to DDR3_DQ[24] -set_location_assignment PIN_AF23 -to DDR3_DQ[25] -set_location_assignment PIN_AJ24 -to DDR3_DQ[26] -set_location_assignment PIN_AK26 -to DDR3_DQ[27] -set_location_assignment PIN_AE23 -to DDR3_DQ[28] -set_location_assignment PIN_AE22 -to DDR3_DQ[29] -set_location_assignment PIN_AG25 -to DDR3_DQ[30] -set_location_assignment PIN_AK27 -to DDR3_DQ[31] -set_location_assignment PIN_W16 -to DDR3_DQS_n[0] -set_location_assignment PIN_W17 -to DDR3_DQS_n[1] -set_location_assignment PIN_AA18 -to DDR3_DQS_n[2] -set_location_assignment PIN_AD19 -to DDR3_DQS_n[3] -set_location_assignment PIN_V16 -to DDR3_DQS_p[0] -set_location_assignment PIN_V17 -to DDR3_DQS_p[1] -set_location_assignment PIN_Y17 -to DDR3_DQS_p[2] -set_location_assignment PIN_AC20 -to DDR3_DQS_p[3] -set_location_assignment PIN_AE16 -to DDR3_ODT -set_location_assignment PIN_AH8 -to DDR3_RAS_n -set_location_assignment PIN_AK21 -to DDR3_RESET_n -set_location_assignment PIN_AG17 -to DDR3_RZQ -set_location_assignment PIN_AJ6 -to DDR3_WE_n -set_location_assignment PIN_AG27 -to FAN_CTRL -set_location_assignment PIN_AB27 -to HSMC_CLKIN_n[1] -set_location_assignment PIN_G15 -to HSMC_CLKIN_n[2] -set_location_assignment PIN_AA26 -to HSMC_CLKIN_p[1] -set_location_assignment PIN_H15 -to HSMC_CLKIN_p[2] -set_location_assignment PIN_E6 -to HSMC_CLKOUT_n[1] -set_location_assignment PIN_A10 -to HSMC_CLKOUT_n[2] -set_location_assignment PIN_E7 -to HSMC_CLKOUT_p[1] -set_location_assignment PIN_A11 -to HSMC_CLKOUT_p[2] -set_location_assignment PIN_J14 -to HSMC_CLK_IN0 -set_location_assignment PIN_AD29 -to HSMC_CLK_OUT0 -set_location_assignment PIN_C10 -to HSMC_D[0] -set_location_assignment PIN_H13 -to HSMC_D[1] -set_location_assignment PIN_C9 -to HSMC_D[2] -set_location_assignment PIN_H12 -to HSMC_D[3] -set_location_assignment PIN_AE2 -to HSMC_GXB_RX_p[0] -set_location_assignment PIN_AC2 -to HSMC_GXB_RX_p[1] -set_location_assignment PIN_AA2 -to HSMC_GXB_RX_p[2] -set_location_assignment PIN_W2 -to HSMC_GXB_RX_p[3] -set_location_assignment PIN_U2 -to HSMC_GXB_RX_p[4] -set_location_assignment PIN_R2 -to HSMC_GXB_RX_p[5] -set_location_assignment PIN_N2 -to HSMC_GXB_RX_p[6] -set_location_assignment PIN_J2 -to HSMC_GXB_RX_p[7] -set_location_assignment PIN_AD4 -to HSMC_GXB_TX_p[0] -set_location_assignment PIN_AB4 -to HSMC_GXB_TX_p[1] -set_location_assignment PIN_Y4 -to HSMC_GXB_TX_p[2] -set_location_assignment PIN_V4 -to HSMC_GXB_TX_p[3] -set_location_assignment PIN_T4 -to HSMC_GXB_TX_p[4] -set_location_assignment PIN_P4 -to HSMC_GXB_TX_p[5] -set_location_assignment PIN_M4 -to HSMC_GXB_TX_p[6] -set_location_assignment PIN_H4 -to HSMC_GXB_TX_p[7] -set_location_assignment PIN_P9 -to HSMC_REF_CLK_p -set_location_assignment PIN_G11 -to HSMC_RX_n[0] -set_location_assignment PIN_J12 -to HSMC_RX_n[1] -set_location_assignment PIN_F10 -to HSMC_RX_n[2] -set_location_assignment PIN_J9 -to HSMC_RX_n[3] -set_location_assignment PIN_K8 -to HSMC_RX_n[4] -set_location_assignment PIN_H7 -to HSMC_RX_n[5] -set_location_assignment PIN_G8 -to HSMC_RX_n[6] -set_location_assignment PIN_F8 -to HSMC_RX_n[7] -set_location_assignment PIN_E11 -to HSMC_RX_n[8] -set_location_assignment PIN_B5 -to HSMC_RX_n[9] -set_location_assignment PIN_D9 -to HSMC_RX_n[10] -set_location_assignment PIN_D12 -to HSMC_RX_n[11] -set_location_assignment PIN_D10 -to HSMC_RX_n[12] -set_location_assignment PIN_B12 -to HSMC_RX_n[13] -set_location_assignment PIN_E13 -to HSMC_RX_n[14] -set_location_assignment PIN_G13 -to HSMC_RX_n[15] -set_location_assignment PIN_F14 -to HSMC_RX_n[16] -set_location_assignment PIN_G12 -to HSMC_RX_p[0] -set_location_assignment PIN_K12 -to HSMC_RX_p[1] -set_location_assignment PIN_G10 -to HSMC_RX_p[2] -set_location_assignment PIN_J10 -to HSMC_RX_p[3] -set_location_assignment PIN_K7 -to HSMC_RX_p[4] -set_location_assignment PIN_J7 -to HSMC_RX_p[5] -set_location_assignment PIN_H8 -to HSMC_RX_p[6] -set_location_assignment PIN_F9 -to HSMC_RX_p[7] -set_location_assignment PIN_F11 -to HSMC_RX_p[8] -set_location_assignment PIN_B6 -to HSMC_RX_p[9] -set_location_assignment PIN_E9 -to HSMC_RX_p[10] -set_location_assignment PIN_E12 -to HSMC_RX_p[11] -set_location_assignment PIN_D11 -to HSMC_RX_p[12] -set_location_assignment PIN_C13 -to HSMC_RX_p[13] -set_location_assignment PIN_F13 -to HSMC_RX_p[14] -set_location_assignment PIN_H14 -to HSMC_RX_p[15] -set_location_assignment PIN_F15 -to HSMC_RX_p[16] -set_location_assignment PIN_AA28 -to HSMC_SCL -set_location_assignment PIN_AE29 -to HSMC_SDA -set_location_assignment PIN_A8 -to HSMC_TX_n[0] -set_location_assignment PIN_D7 -to HSMC_TX_n[1] -set_location_assignment PIN_F6 -to HSMC_TX_n[2] -set_location_assignment PIN_C5 -to HSMC_TX_n[3] -set_location_assignment PIN_C4 -to HSMC_TX_n[4] -set_location_assignment PIN_E2 -to HSMC_TX_n[5] -set_location_assignment PIN_D4 -to HSMC_TX_n[6] -set_location_assignment PIN_B3 -to HSMC_TX_n[7] -set_location_assignment PIN_D1 -to HSMC_TX_n[8] -set_location_assignment PIN_C2 -to HSMC_TX_n[9] -set_location_assignment PIN_B1 -to HSMC_TX_n[10] -set_location_assignment PIN_A3 -to HSMC_TX_n[11] -set_location_assignment PIN_A5 -to HSMC_TX_n[12] -set_location_assignment PIN_B7 -to HSMC_TX_n[13] -set_location_assignment PIN_B8 -to HSMC_TX_n[14] -set_location_assignment PIN_B11 -to HSMC_TX_n[15] -set_location_assignment PIN_A13 -to HSMC_TX_n[16] -set_location_assignment PIN_A9 -to HSMC_TX_p[0] -set_location_assignment PIN_E8 -to HSMC_TX_p[1] -set_location_assignment PIN_G7 -to HSMC_TX_p[2] -set_location_assignment PIN_D6 -to HSMC_TX_p[3] -set_location_assignment PIN_D5 -to HSMC_TX_p[4] -set_location_assignment PIN_E3 -to HSMC_TX_p[5] -set_location_assignment PIN_E4 -to HSMC_TX_p[6] -set_location_assignment PIN_C3 -to HSMC_TX_p[7] -set_location_assignment PIN_E1 -to HSMC_TX_p[8] -set_location_assignment PIN_D2 -to HSMC_TX_p[9] -set_location_assignment PIN_B2 -to HSMC_TX_p[10] -set_location_assignment PIN_A4 -to HSMC_TX_p[11] -set_location_assignment PIN_A6 -to HSMC_TX_p[12] -set_location_assignment PIN_C7 -to HSMC_TX_p[13] -set_location_assignment PIN_C8 -to HSMC_TX_p[14] -set_location_assignment PIN_C12 -to HSMC_TX_p[15] -set_location_assignment PIN_B13 -to HSMC_TX_p[16] -set_location_assignment PIN_AH2 -to IRDA_RXD -set_location_assignment PIN_AE9 -to KEY[0] -set_location_assignment PIN_AE12 -to KEY[1] -set_location_assignment PIN_AD9 -to KEY[2] -set_location_assignment PIN_AD11 -to KEY[3] -set_location_assignment PIN_AF10 -to LED[0] -set_location_assignment PIN_AD10 -to LED[1] -set_location_assignment PIN_AE11 -to LED[2] -set_location_assignment PIN_AD7 -to LED[3] -set_location_assignment PIN_AF14 -to OSC_50_B3B -set_location_assignment PIN_AA16 -to OSC_50_B4A -set_location_assignment PIN_Y26 -to OSC_50_B5B -set_location_assignment PIN_K14 -to OSC_50_B8A -set_location_assignment PIN_W22 -to PCIE_PERST_n -set_location_assignment PIN_W21 -to PCIE_WAKE_n -set_location_assignment PIN_AD27 -to RESET_n -set_location_assignment PIN_AE26 -to SI5338_SCL -set_location_assignment PIN_AJ29 -to SI5338_SDA -set_location_assignment PIN_W25 -to SW[0] -set_location_assignment PIN_V25 -to SW[1] -set_location_assignment PIN_AC28 -to SW[2] -set_location_assignment PIN_AC29 -to SW[3] -set_location_assignment PIN_AF8 -to TEMP_CS_n -set_location_assignment PIN_AG7 -to TEMP_DIN -set_location_assignment PIN_AG1 -to TEMP_DOUT -set_location_assignment PIN_AF9 -to TEMP_SCLK -set_location_assignment PIN_AF13 -to USB_B2_CLK -set_location_assignment PIN_AK28 -to USB_B2_DATA[0] -set_location_assignment PIN_AD20 -to USB_B2_DATA[1] -set_location_assignment PIN_AD21 -to USB_B2_DATA[2] -set_location_assignment PIN_Y19 -to USB_B2_DATA[3] -set_location_assignment PIN_AA20 -to USB_B2_DATA[4] -set_location_assignment PIN_AH27 -to USB_B2_DATA[5] -set_location_assignment PIN_AF25 -to USB_B2_DATA[6] -set_location_assignment PIN_AC22 -to USB_B2_DATA[7] -set_location_assignment PIN_AJ4 -to USB_EMPTY -set_location_assignment PIN_AK3 -to USB_FULL -set_location_assignment PIN_AE14 -to USB_OE_n -set_location_assignment PIN_AJ5 -to USB_RD_n -set_location_assignment PIN_AD14 -to USB_RESET_n -set_location_assignment PIN_AK4 -to USB_SCL -set_location_assignment PIN_AE13 -to USB_SDA -set_location_assignment PIN_AK6 -to USB_WR_n -set_location_assignment PIN_AE28 -to VGA_B[0] -set_location_assignment PIN_Y23 -to VGA_B[1] -set_location_assignment PIN_Y24 -to VGA_B[2] -set_location_assignment PIN_AG28 -to VGA_B[3] -set_location_assignment PIN_AF28 -to VGA_B[4] -set_location_assignment PIN_V23 -to VGA_B[5] -set_location_assignment PIN_W24 -to VGA_B[6] -set_location_assignment PIN_AF29 -to VGA_B[7] -set_location_assignment PIN_AH3 -to VGA_BLANK_n -set_location_assignment PIN_W20 -to VGA_CLK -set_location_assignment PIN_Y21 -to VGA_G[0] -set_location_assignment PIN_AA25 -to VGA_G[1] -set_location_assignment PIN_AB26 -to VGA_G[2] -set_location_assignment PIN_AB22 -to VGA_G[3] -set_location_assignment PIN_AB23 -to VGA_G[4] -set_location_assignment PIN_AA24 -to VGA_G[5] -set_location_assignment PIN_AB25 -to VGA_G[6] -set_location_assignment PIN_AE27 -to VGA_G[7] -set_location_assignment PIN_AD12 -to VGA_HS -set_location_assignment PIN_AG5 -to VGA_R[0] -set_location_assignment PIN_AA12 -to VGA_R[1] -set_location_assignment PIN_AB12 -to VGA_R[2] -set_location_assignment PIN_AF6 -to VGA_R[3] -set_location_assignment PIN_AG6 -to VGA_R[4] -set_location_assignment PIN_AJ2 -to VGA_R[5] -set_location_assignment PIN_AH5 -to VGA_R[6] -set_location_assignment PIN_AJ1 -to VGA_R[7] -set_location_assignment PIN_AG2 -to VGA_SYNC_n -set_location_assignment PIN_AC12 -to VGA_VS - - -#============================================================ -set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS -to HSMC_REF_CLK_p - -set_global_assignment -name VERILOG_FILE SoCKitTop.v -set_global_assignment -name VERILOG_FILE JTAGUART.v -set_global_assignment -name VERILOG_FILE BlarneyComponent.v -set_global_assignment -name VERILOG_FILE Top.v -set_global_assignment -name VERILOG_FILE "Src/Top-Verilog/Top.v" -set_global_assignment -name QIP_FILE SoC/synthesis/SoC.qip -set_global_assignment -name SDC_FILE SoCKitTop.sdc diff --git a/work/CheckFPGA_Sums_Parallel/SoCKitTop.sdc b/work/CheckFPGA_Sums_Parallel/SoCKitTop.sdc deleted file mode 100644 index 865a053..0000000 --- a/work/CheckFPGA_Sums_Parallel/SoCKitTop.sdc +++ /dev/null @@ -1,85 +0,0 @@ - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -period 20 [get_ports OSC_50_B3B] -create_clock -period 20 [get_ports OSC_50_B4A] -create_clock -period 20 [get_ports OSC_50_B5B] -create_clock -period 20 [get_ports OSC_50_B8A] - - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -##************************************************************** - -#************************************************************** -# Set False Path -#************************************************************** - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - - - diff --git a/work/CheckFPGA_Sums_Parallel/SoCKitTop.v b/work/CheckFPGA_Sums_Parallel/SoCKitTop.v deleted file mode 100644 index a825c59..0000000 --- a/work/CheckFPGA_Sums_Parallel/SoCKitTop.v +++ /dev/null @@ -1,219 +0,0 @@ -// ============================================================================ -// Copyright (c) 2013 by Terasic Technologies Inc. -// ============================================================================ -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// ============================================================================ -// -// Terasic Technologies Inc -// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan -// -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// ============================================================================ -//Date: Mon Jul 1 14:21:10 2013 -// ============================================================================ - -//`define ENABLE_DDR3 -//`define ENABLE_HPS -//`define ENABLE_HSMC - -module SocKit_golden_top( - - ///////// AUD ///////// - input AUD_ADCDAT, - inout AUD_ADCLRCK, - inout AUD_BCLK, - output AUD_DACDAT, - inout AUD_DACLRCK, - output AUD_I2C_SCLK, - inout AUD_I2C_SDAT, - output AUD_MUTE, - output AUD_XCK, - -`ifdef ENABLE_DDR3 - ///////// DDR3 ///////// - output [14:0] DDR3_A, - output [2:0] DDR3_BA, - output DDR3_CAS_n, - output DDR3_CKE, - output DDR3_CK_n, - output DDR3_CK_p, - output DDR3_CS_n, - output [3:0] DDR3_DM, - inout [31:0] DDR3_DQ, - inout [3:0] DDR3_DQS_n, - inout [3:0] DDR3_DQS_p, - output DDR3_ODT, - output DDR3_RAS_n, - output DDR3_RESET_n, - input DDR3_RZQ, - output DDR3_WE_n, -`endif /*ENABLE_DDR3*/ - - ///////// FAN ///////// - output FAN_CTRL, - -`ifdef ENABLE_HPS - ///////// HPS ///////// - input HPS_CONV_USB_n, - output [14:0] HPS_DDR3_A, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_n, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_n, - output HPS_DDR3_CK_p, - output HPS_DDR3_CS_n, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_n, - inout [3:0] HPS_DDR3_DQS_p, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_n, - output HPS_DDR3_RESET_n, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_n, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_n, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout [3:0] HPS_FLASH_DATA, - output HPS_FLASH_DCLK, - output HPS_FLASH_NCSO, - inout HPS_GSENSOR_INT, - inout HPS_I2C_CLK, - inout HPS_I2C_SDA, - inout [3:0] HPS_KEY, - inout HPS_LCM_BK, - output HPS_LCM_D_C, - output HPS_LCM_RST_N, - input HPS_LCM_SPIM_CLK, - output HPS_LCM_SPIM_MOSI, - output HPS_LCM_SPIM_SS, - output [3:0] HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - output HPS_SPIM_SS, - input [3:0] HPS_SW, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, -`endif /*ENABLE_HPS*/ - -`ifdef ENABLE_HSMC - ///////// HSMC ///////// - input [2:1] HSMC_CLKIN_n, - input [2:1] HSMC_CLKIN_p, - output [2:1] HSMC_CLKOUT_n, - output [2:1] HSMC_CLKOUT_p, - output HSMC_CLK_IN0, - output HSMC_CLK_OUT0, - inout [3:0] HSMC_D, - input [7:0] HSMC_GXB_RX_p, - output [7:0] HSMC_GXB_TX_p, - input HSMC_REF_CLK_p, - inout [16:0] HSMC_RX_n, - inout [16:0] HSMC_RX_p, - output HSMC_SCL, - inout HSMC_SDA, - inout [16:0] HSMC_TX_n, - inout [16:0] HSMC_TX_p, -`endif /*ENABLE_HSMC*/ - - ///////// IRDA ///////// - input IRDA_RXD, - - ///////// KEY ///////// - input [3:0] KEY, - - ///////// LED ///////// - output [3:0] LED, - - ///////// OSC ///////// - input OSC_50_B3B, - input OSC_50_B4A, - input OSC_50_B5B, - input OSC_50_B8A, - - ///////// PCIE ///////// - input PCIE_PERST_n, - output PCIE_WAKE_n, - - ///////// RESET ///////// - input RESET_n, - - ///////// SI5338 ///////// - inout SI5338_SCL, - inout SI5338_SDA, - - ///////// SW ///////// - input [3:0] SW, - - ///////// TEMP ///////// - output TEMP_CS_n, - output TEMP_DIN, - input TEMP_DOUT, - output TEMP_SCLK, - - ///////// USB ///////// - input USB_B2_CLK, - inout [7:0] USB_B2_DATA, - output USB_EMPTY, - output USB_FULL, - input USB_OE_n, - input USB_RD_n, - input USB_RESET_n, - inout USB_SCL, - inout USB_SDA, - input USB_WR_n, - - ///////// VGA ///////// - output [7:0] VGA_B, - output VGA_BLANK_n, - output VGA_CLK, - output [7:0] VGA_G, - output VGA_HS, - output [7:0] VGA_R, - output VGA_SYNC_n, - output VGA_VS -); - - assign LED = 10; - - SoC soc ( - .clk_clk(OSC_50_B3B), - .reset_reset_n(RESET_n) - ); - -endmodule diff --git a/work/CheckFPGA_Sums_Parallel/Src/Makefile b/work/CheckFPGA_Sums_Parallel/Src/Makefile deleted file mode 100644 index 12f460b..0000000 --- a/work/CheckFPGA_Sums_Parallel/Src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -.PHONY: all -all: - blc Main.hs -o Main - ./Main - -clean: - rm -rf *.o *.hi Main Top-Verilog diff --git a/work/CheckFPGA_Sums_Parallel/report.ods b/work/CheckFPGA_Sums_Parallel/report.ods deleted file mode 100644 index 5691e07..0000000 Binary files a/work/CheckFPGA_Sums_Parallel/report.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums_Parallel/report_fmax.ods b/work/CheckFPGA_Sums_Parallel/report_fmax.ods deleted file mode 100644 index 4de0823..0000000 Binary files a/work/CheckFPGA_Sums_Parallel/report_fmax.ods and /dev/null differ diff --git a/work/CheckFPGA_Sums_Parallel/report_util.ods b/work/CheckFPGA_Sums_Parallel/report_util.ods deleted file mode 100644 index 4a76e8a..0000000 Binary files a/work/CheckFPGA_Sums_Parallel/report_util.ods and /dev/null differ diff --git a/work/CheckOriginal/Check_Parallel.hs b/work/CheckOriginal/Check_Parallel.hs deleted file mode 100644 index a5d2680..0000000 --- a/work/CheckOriginal/Check_Parallel.hs +++ /dev/null @@ -1,122 +0,0 @@ --- Can now bit width of input from type so that we can generate all test cases exhaustively - -{-# LANGUAGE GADTs #-} -{-# LANGUAGE ConstraintKinds #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE UndecidableInstances #-} - -import Blarney -import Check.Generator - -class Testable a where - test :: a -> (Bit 1) - -instance Testable (Bit 1) where - test b = b - -instance (Generator a, Testable b) => Testable (a -> b) where - test = testFunction - -{- -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: SizedBits a => (a -> Prop) -> Prop - ForallList :: SizedBits a => Integer -> ([a] -> Prop) -> Prop --} -genListInputs :: Integer -> Integer -> [[Integer]] -genListInputs maxDepth currLength - | currLength <= 0 = [[]] - | otherwise = []:[ x:xs | x <- [0 .. maxDepth], xs <- (genListInputs maxDepth (currLength-1))] - -applyToProp :: (Prop, Action ()) -> [(Prop, Action ())] -applyToProp prop@(Assert _, _) = [prop] -applyToProp (prop@(Forall f), disp) = - [(f (unpack (constant x)), disp >> display_ x ", ") | x <- [0 .. (getMaxInegerSize prop)]] -applyToProp (prop@(ForallList maxLength f), disp) = - [(f (map (\x -> (unpack (constant x))) xs), disp >> display_ (fshowList xs) ", ") | xs <- (genListInputs (getMaxInegerSize prop) maxLength)] - -getMaxInegerSize :: Prop -> Integer -getMaxInegerSize prop = let size = (sizeProp prop) in - if size < 2 then 1 else (2 ^ size) - 1 -sizeForall :: Prop -> Integer -sizeForall (Assert _) = 1 -sizeForall (Forall (_ :: a -> Prop)) = toInteger (valueOf @(SizeOf a)) -sizeForall (ForallList _ (_ :: [a] -> Prop)) = toInteger (valueOf @(SizeOf a)) - --g :: (Bits a, KnownNat (SizeOf a)) => Integer -> a - --g x = (unpack (constant (min x size)) - --size = valueOf @(SizeOf a) - -sizeProp :: Prop -> Int -sizeProp (Assert _) = 1 -sizeProp (Forall (_ :: a -> Prop)) = valueOf @(SizeOf a) -sizeProp (ForallList _ (_ :: [a] -> Prop)) = valueOf @(SizeOf a) - -genInputs :: [(Prop, Action ())] -> [(Prop, Action ())] -genInputs [] = [] -genInputs props@((Assert _, _):_) = props -genInputs props@((Forall _, _):_) = - genInputs (concatMap (applyToProp) props) -genInputs props@((ForallList _ _, _):_) = - genInputs (concatMap (applyToProp) props) - -displayProps :: [(Prop, Action ())] -> Action () -displayProps [] = finish -displayProps ((Assert p, disp):props) = do - _ <- display_ "Test with inputs: " - disp - _ <- display "\tresult: " (p) - displayProps props -displayProps _ = noAction - -checkTwo :: Prop -> Action () -checkTwo prop = do - let initial = [(prop, noAction)] - let checkCases = (genInputs initial) - displayProps checkCases - -check :: Prop -> Module() -check prop = do - let testSeq = (checkTwo prop) - - --globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - testSeq - - --globalTime <== globalTime.val + 1 - --display "Time: " (globalTime.val) - - - -twoSort :: KnownNat n => (Bit n, Bit n) -> (Bit n, Bit n) -twoSort (a :: Bit n, b) = let halfSize = constant (toInteger (valueOf @(n))) in - (b - a) + halfSize .>=. halfSize ? ((a, b), (b, a)) ---twoSort (a, b) = a .<. b ? ((a, b), (b, a)) - -bubble :: KnownNat n => [Bit n] -> [Bit n] -bubble [] = [] -bubble [x] = [x] -bubble (x:y:rest) = bubble (small:rest) ++ [big] - where (small, big) = twoSort (x, y) - -sort :: KnownNat n => [Bit n] -> [Bit n] -sort [] = [] -sort (x:xs) = smallest : sort rest - where (smallest:rest) = bubble (x:xs) - -isSorted :: KnownNat n => [Bit n] -> Bit 1 -isSorted [] = 1 -isSorted [_] = 1 -isSorted (x1:x2:xs) = (x1 .<=. x2) .&. isSorted (x2:xs) - - - -top :: Module () -top = do - --let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 4)-b.==.b-a) - let propSort = ForallList 4 \a -> Assert (isSorted (sort (a::[Bit 1]))) - check propSort - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Check_Serial.hs b/work/CheckOriginal/Check_Serial.hs deleted file mode 100644 index 4cf217e..0000000 --- a/work/CheckOriginal/Check_Serial.hs +++ /dev/null @@ -1,122 +0,0 @@ --- Create a series class that allows all the inputs up to a depth to be generated - -{-# LANGUAGE GADTs #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE UndecidableInstances #-} -{-# LANGUAGE ConstraintKinds #-} - -import Blarney -import Check.Generator - -data TestBench = TestBench - { runTest :: Action () - , increment :: Action () - , isDone :: Bit 1 - } deriving (Generic, Interface) - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: SizedBits a => String -> (a -> Prop) -> Prop - - -makeAssertTestBench :: (Bit 1) -> Action () -> TestBench -makeAssertTestBench result dispValues = - TestBench { runTest = when (inv result) do - dispValues >> display "failed the test." >> finish - , increment = noAction - , isDone = 1 - } - -doActionList :: [Action ()] -> Action () -doActionList xs = foldr (>>) noAction xs - -extractDones :: [TestBench] -> [Bit 1] -extractDones [] = [] -extractDones (tb:tbs) = (tb.isDone):(extractDones tbs) - - -runAllTbs :: [TestBench] -> Action () -runAllTbs [] = noAction -runAllTbs (tb:tbs) = tb.runTest >> (runAllTbs tbs) - - -createIncrementAction :: SizedBits a => (TestBench, Reg a) -> Action () -createIncrementAction (tb, register) = do - if (bitsGen.isLast $ register.val) - then - if tb.isDone - then - noAction - else do - (register <== bitsGen.initial) - tb.increment - else - register <== (bitsGen.next $ register.val) - - -displayVarAndAbove :: SizedBits a => (String, Reg a) -> Action () -> Action () -displayVarAndAbove (name, register) dispAbove = do - dispAbove - display_ name "=" (pack (register.val)) ", " - - -{-Create the base TestBench here-} -checkGen :: (Prop, Action ()) -> Module (TestBench) -checkGen ((Assert p), dispValues) = do - return (makeAssertTestBench p dispValues) -checkGen ((Forall name f), dispValues) = do - inputs <- mapM makeReg [bitsGen.initial] - tbs <- mapM checkGen (map (\r -> (f (r.val), displayVarAndAbove (name, r) dispValues)) inputs) - let combined = zip tbs inputs - let isDoneComputed = andList $ (map (\myin -> bitsGen.isLast $ myin.val) inputs)++(extractDones tbs) - - return TestBench { runTest = runAllTbs tbs - , increment = if isDoneComputed then noAction else (doActionList (map createIncrementAction combined)) - , isDone = isDoneComputed - } - - -check :: Prop -> Module(Bit 1) -check prop = do - tb <- (checkGen (prop, noAction)) - - globalTime :: Reg (Bit 32) <- makeReg 0 - testComplete :: Reg (Bit 1) <- makeReg 0 - always do - globalTime <== globalTime.val + 1 - when (inv (testComplete.val)) do - testComplete <== tb.isDone - tb.increment - tb.runTest - --display "Time: " (globalTime.val) - when (tb.isDone) do - display "Test pass" - return (testComplete.val) - - - -firstHot :: KnownNat n => Bit n -> Bit n -firstHot x = x .&. ((inv x) .+. 1); - -top :: Module () -top = do - --let propSubComm = Forall "A" \a -> Forall "B" \b -> Assert ((a :: Bit 2)-b.==.b-a) - let prop_OneIsHot = Forall "A" \x -> Assert (countOnes (firstHot (x :: Bit 4)) .==. ((x .==. 0) ? (0, 1))) - let prop_HotBitCommon = Forall "B" \x -> Assert ((x :: Bit 4) .&. (firstHot x) .==. (firstHot x)) - let prop_HotBitFirst = Forall "C" \x -> Assert ((x :: Bit 4) .&. ((firstHot x) - 1) .==. 0) - - t1Complete <- check prop_OneIsHot - t2Complete <- check prop_HotBitCommon - t3Complete <- check prop_HotBitFirst - --subComplete <- check propSubComm - - let complete = t1Complete .&. t2Complete .&. t3Complete - --let complete = subComplete - - always do - when complete do - finish - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Generator.hs b/work/CheckOriginal/Generator.hs deleted file mode 100644 index bc46dab..0000000 --- a/work/CheckOriginal/Generator.hs +++ /dev/null @@ -1,67 +0,0 @@ --- Problem is that we cannot test aribtrary data structures (eg. that the user has defined) --- Solution is to come up with a generator datatype which the user can specify for custom types and these can then be tested --- Two possiblilities of stateful vs stateless generator. - --- Do we need to support user defined data? --- Need some way to guarantee that 't' can be stored in a register(s?), how to do for lists? - -{-# LANGUAGE MultiParamTypeClasses #-} -{-# LANGUAGE FlexibleInstances #-} -{-# LANGUAGE FunctionalDependencies #-} -{-# LANGUAGE BlockArguments #-} -{-# LANGUAGE DataKinds #-} -{-# LANGUAGE NoImplicitPrelude #-} -{-# LANGUAGE DeriveGeneric #-} -{-# LANGUAGE DeriveAnyClass #-} -{-# LANGUAGE ConstraintKinds #-} -{-# LANGUAGE UndecidableInstances #-} - -module Check.Generator where - -import Blarney - -type SizedBits a = (Bits a, KnownNat (SizeOf a)) - - - - - -{- -class Generator t where - initial :: t - next :: t -> t - isLast :: t -> Bit 1 - -instance KnownNat n => Generator (Bit n) where - initial = makeReg (constant 0) - next = \prev -> prev .+. 1 - isLast = \value -> value .==. ones - -instance (SizedBits a) => Generator a where - initial = makeReg (unpack (constant 0)) - next = \prev -> unpack $ (pack prev) .+. 1 - isLast = \value -> (pack value) .==. ones - -instance (SizedBits a) => Generator ([a]) where - initial = makeReg ([unpack (constant 0)]) - next = \prev -> unpack $ (pack prev) .+. 1 - isLast = \value -> (pack value) .==. ones --} -{- -data GeneratorState t = GeneratorState - { peek :: t - , isLast :: Bit 1 - , reset :: Action () - , consume :: Action () - } deriving (Generic, Interface) - - -bitGen :: Bits a => Module (GeneratorState a) -bitGen = do - - Generator { - peek = constant 0, - next = \prev -> prev .+. 1, - isLast = \value -> value .==. ones -} --} \ No newline at end of file diff --git a/work/CheckOriginal/Old/Check_05-11-19.hs b/work/CheckOriginal/Old/Check_05-11-19.hs deleted file mode 100644 index 0d736f9..0000000 --- a/work/CheckOriginal/Old/Check_05-11-19.hs +++ /dev/null @@ -1,36 +0,0 @@ -import Blarney - -data Prop = Assert (Bit 1) | Forall (Bit 3 -> Prop) - -check :: Integer -> Prop -> [Action ()] -check depth prop = (checkGenerate "" depth 0 prop) - where - -- String is just for debugging, Integer tracks what case we are on - checkGenerate :: String -> Integer -> Integer -> Prop -> [Action ()] - checkGenerate s _ _ (Assert prop) = [do - display "Test" s ", result: " (prop) - ] - checkGenerate s maxDepth currDepth (Forall f) - | currDepth >= maxDepth = appliedForall - | otherwise = appliedForall ++ checkGenerate s maxDepth (currDepth+1) (Forall f) - where - appliedForall = checkGenerate (s ++ " " ++ show currDepth) maxDepth 0 (f (fromInteger currDepth)) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert (a-b.==.b-a) - - let testSeq = Par (map Action (check (2^3-1) propSubComm)) - done <- run (reg 1 0) testSeq - - globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - (when done finish) - - globalTime <== globalTime.val + 1 - display "Time: " (globalTime.val) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_10-11-19_mapLists.hs b/work/CheckOriginal/Old/Check_10-11-19_mapLists.hs deleted file mode 100644 index ba35fd7..0000000 --- a/work/CheckOriginal/Old/Check_10-11-19_mapLists.hs +++ /dev/null @@ -1,52 +0,0 @@ -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, Num a) => (a -> Prop) -> Prop - -genInputs :: Integer -> [Prop] -> [Prop] -> [Prop] -genInputs _ [] finalProps = finalProps -genInputs n ((Assert p):xs) finalProps = genInputs n xs ((Assert p):finalProps) -genInputs n ((Forall f):xs) finalProps = genInputs n (xs++(map f (map fromInteger [0 .. n]))) finalProps - -displayProp :: Prop -> Action () -displayProp (Assert p) = do - display "Test, result: " (p) - -checkTwo :: Integer -> Prop -> [Action ()] -checkTwo depth prop = map displayProp (genInputs depth [prop] []) - -check :: Integer -> Prop -> [Action ()] -check depth prop = (checkGenerate "" depth 0 prop) - where - -- String is just for debugging, Integer tracks what case we are on - checkGenerate :: String -> Integer -> Integer -> Prop -> [Action ()] - checkGenerate s _ _ (Assert prop) = [do - display "Test" s ", result: " (prop) - ] - checkGenerate s maxDepth currDepth (Forall f) - | currDepth >= maxDepth = appliedForall - | otherwise = appliedForall ++ checkGenerate s maxDepth (currDepth+1) (Forall f) - where - appliedForall = checkGenerate (s ++ " " ++ show currDepth) maxDepth 0 (f (fromInteger currDepth)) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert ((a:: Bit 4)-(b:: Bit 4).==.b-a) - - let testSeq = Par (map Action (checkTwo (2^3-1) propSubComm)) - done <- run (reg 1 0) testSeq - - globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - (when done finish) - - globalTime <== globalTime.val + 1 - display "Time: " (globalTime.val) - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_11-11-19_registerError.txt b/work/CheckOriginal/Old/Check_11-11-19_registerError.txt deleted file mode 100644 index 0841e36..0000000 --- a/work/CheckOriginal/Old/Check_11-11-19_registerError.txt +++ /dev/null @@ -1,20 +0,0 @@ -Check.hs:49:51: error: - • Could not deduce (Val (Module (Reg a)) a1) - arising from a use of ‘val’ - from the context: Bits a - bound by the type signature for: - checkSeq :: forall a. - Bits a => - Prop -> [Module (Reg a)] -> Action () - at Check.hs:47:1-59 - or from: Bits a1 - bound by a pattern with constructor: - Forall :: forall a. Bits a => (a -> Prop) -> Prop, - in an equation for ‘checkSeq’ - at Check.hs:49:11-18 - • In the second argument of ‘(.)’, namely ‘val’ - In the first argument of ‘f’, namely ‘(reg . val)’ - In the first argument of ‘checkSeq’, namely ‘(f (reg . val))’ - | -49 | checkSeq (Forall f) (reg:regs) = checkSeq (f (reg.val)) regs - | ^^^ \ No newline at end of file diff --git a/work/CheckOriginal/Old/Check_20-11_ListsCheck.hs b/work/CheckOriginal/Old/Check_20-11_ListsCheck.hs deleted file mode 100644 index f6883b9..0000000 --- a/work/CheckOriginal/Old/Check_20-11_ListsCheck.hs +++ /dev/null @@ -1,66 +0,0 @@ --- First attempt at generating lists (a lot of functions used for this!!) - -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, KnownNat (SizeOf a)) => (a -> Prop) -> Prop - ForallList :: (Bits a, KnownNat (SizeOf a)) => Integer -> ([a] -> Prop) -> Prop - -concatHelp :: [[Integer]] -> Integer -> [[Integer]] -concatHelp [[]] numToPrepend = [[numToPrepend]] -concatHelp (xs:xss) numToPrepend = (numToPrepend:xs):(concatHelp xss numToPrepend) - -genPermutations :: Integer -> Integer -> [[Integer]] -genPermutations maxDepth 0 = [[]] -genPermutations maxDepth length = concatMap (concatHelp (genPermutations maxDepth (length-1))) [0 .. maxDepth] - -genListInputs :: Integer -> Integer -> Integer -> [[Integer]] -genListInputs maxLength maxDepth currLength - | maxLength == currLength = genPermutations maxDepth currLength - | otherwise = (genPermutations maxDepth currLength) ++ (genListInputs maxLength maxDepth (currLength+1)) - -applyToProp :: Integer -> Prop -> [Prop] -applyToProp n (Forall f) = map f (map (\x -> unpack (constant x)) [0 .. n]) -applyToProp n (ForallList maxLength f) = map f (map (\x -> map (\y -> unpack (constant y)) x) (genListInputs maxLength n 0)) - -genInputs :: Integer -> [Prop] -> [Prop] -genInputs _ [] = [] -genInputs n props@((Assert _):xs) = props -genInputs n props@((Forall _):xs) = - genInputs n (concat (map (applyToProp n) props)) -genInputs n props@((ForallList _ _):xs) = - genInputs n (concatMap (applyToProp n) props) - -displayProps :: [Prop] -> Action () -displayProps [] = finish -displayProps ((Assert p):props) = do - display "Test, result: " (p) - displayProps props - -checkTwo :: Integer -> Prop -> Action () -checkTwo depth prop = displayProps (genInputs depth [prop]) - -check :: Integer -> Prop -> Module() -check depth prop = do - let testSeq = (checkTwo (2^3-1) prop) - - --globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - testSeq - - --globalTime <== globalTime.val + 1 - --display "Time: " (globalTime.val) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 4)-b.==.b-a) - check (2^3-1) propSubComm - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Generator_25-11.hs b/work/CheckOriginal/Old/Check_Generator_25-11.hs deleted file mode 100644 index f4a3427..0000000 --- a/work/CheckOriginal/Old/Check_Generator_25-11.hs +++ /dev/null @@ -1,134 +0,0 @@ --- Generalized TestBench to only provide the required functionality --- Learned more about GADT and constructing them - -{-# LANGUAGE GADTs #-} - -import Blarney - -data TestBench where - Empty :: Action () -> TestBench - -- Display result - Gen :: Action () -> Action () -> (Bit 1) -> TestBench - -- Display Increment Is Done - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, KnownNat (SizeOf a)) => String -> (a -> Prop) -> Prop - -doActionList :: [Action ()] -> Action () -doActionList [] = noAction -doActionList (x:xs) = do - x - doActionList xs - -extractDones :: [TestBench] -> [Bit 1] -extractDones [] = [] -extractDones ((Empty _):gs) = (constant 1):(extractDones gs) -extractDones ((Gen _ _ done):gs) = done:(extractDones gs) - -extractIncrements :: [TestBench] -> [Action ()] -extractIncrements [] = [] -extractIncrements ((Empty _):gs) = (noAction):(extractIncrements gs) -extractIncrements ((Gen _ increment _):gs) = increment:(extractIncrements gs) - -{-Increment action generating functions-} -incReg :: (Bits a, KnownNat (SizeOf a)) => a -> a -incReg x = unpack ((pack x) + 1) - -createIncrementAction :: (Bits a, KnownNat (SizeOf a)) => (TestBench, Reg a) -> Action () -createIncrementAction ((Empty _), reg) = do - if (reg.val === ones) - then do - noAction - else - (reg <== (incReg (reg.val))) -createIncrementAction ((Gen _ increment isDone), reg) = do - if (reg.val === ones) - then - if isDone - then - noAction - else do - (reg <== (unpack 0)) - increment - else - (reg <== (incReg (reg.val))) - -{-Display action generating functions-} -displayProp :: TestBench -> Action () -displayProp (Empty disp) = disp -displayProp (Gen disp _ _) = disp - -displayVarAndBelow :: (Bits a, KnownNat (SizeOf a)) => String -> (TestBench, Reg a) -> Action () -displayVarAndBelow name (g, x) = do - display "Set " name " to " (pack (x.val)) " " - displayProp g - - -{-Create the base TestBench here-} -checkGen :: Prop -> Module (TestBench) -checkGen (Assert p) = do - return (Empty (display "Test result: " p)) -checkGen (Forall name f) = do - inputs <- mapM makeReg (map unpack [0]) - gs <- mapM checkGen (map (\r -> f (r.val)) inputs) - let combined = zip gs inputs - let displayValue = doActionList (map (displayVarAndBelow name) combined) - let isDone = andList ((map (\input -> (input.val === ones)) inputs)++(extractDones gs)) - let increment = if isDone then noAction else (doActionList (map createIncrementAction combined)) - return (Gen displayValue increment isDone) - - - -isFinished :: TestBench -> Bit 1 -isFinished (Empty _) = 1 -isFinished (Gen _ _ isDone) = isDone - - -incrementGen :: TestBench -> Action () -incrementGen (Empty _) = noAction -incrementGen (Gen _ increment _) = increment - -check :: Prop -> Module(Bit 1) -check prop = do - g <- (checkGen prop) - - globalTime :: Reg (Bit 32) <- makeReg 0 - testComplete :: Reg (Bit 1) <- makeReg 0 - always do - --(when (globalTime.val .==. 2000) finish) - globalTime <== globalTime.val + 1 - when (inv (testComplete.val)) do - testComplete <== isFinished g - incrementGen g - displayProp g - --display "Time: " (globalTime.val) - return (testComplete.val) - - - -firstHot :: KnownNat n => Bit n -> Bit n -firstHot x = x .&. ((inv x) .+. 1); - -top :: Module () -top = do - let propSubComm = Forall "A" \a -> Forall "B" \b -> Assert ((a :: Bit 2)-b.==.b-a) - --let prop_OneIsHot = Forall \x -> Assert (countOnes (firstHot (x :: Bit 4)) .==. ((x .==. 0) ? (0, 1))) - --let prop_HotBitCommon = Forall \x -> Assert ((x :: Bit 4) .&. (firstHot x) .==. (firstHot x)) - --let prop_HotBitFirst = Forall \x -> Assert ((x :: Bit 4) .&. ((firstHot x) - 1) .==. 0) - - --t1Complete <- check prop_OneIsHot - --t2Complete <- check prop_HotBitCommon - --t3Complete <- check prop_HotBitFirst - subComplete <- check propSubComm - - --let complete = t1Complete .&. t2Complete .&. t3Complete - let complete = subComplete - - always do - when complete do - finish - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Par_12-11-19.hs b/work/CheckOriginal/Old/Check_Par_12-11-19.hs deleted file mode 100644 index 373aaa8..0000000 --- a/work/CheckOriginal/Old/Check_Par_12-11-19.hs +++ /dev/null @@ -1,65 +0,0 @@ --- Add list comprehension to simplify functions --- Take integer depth to enable going to some depth (dont know how to get size of a) - -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, KnownNat (SizeOf a)) => (a -> Prop) -> Prop - - -applyToProp :: Integer -> Prop -> [Prop] -applyToProp n (Forall f) = map f (map (\x -> unpack (constant x)) [0 .. n]) - -genInputs :: Integer -> [Prop] -> [Prop] -genInputs _ [] = [] -genInputs n ((Assert p):xs) = ((Assert p):xs) -genInputs n ((Forall f):xs) = - genInputs n (concat (map (applyToProp n) ((Forall f):xs))) - -displayProp :: Prop -> Action () -displayProp (Assert p) = do - display "Test, result: " (p) - -checkTwo :: Integer -> Prop -> [Action ()] -checkTwo depth prop = map displayProp (genInputs depth [prop]) - -checkThree :: Integer -> Prop -> [Action ()] -checkThree depth prop = (checkGenerate "" depth 0 prop) - where - -- String is just for debugging, Integer tracks what case we are on - checkGenerate :: String -> Integer -> Integer -> Prop -> [Action ()] - checkGenerate s _ _ (Assert prop) = [do - display "Test" s ", result: " (prop) - ] - checkGenerate s maxDepth currDepth (Forall f) - | currDepth >= maxDepth = appliedForall - | otherwise = appliedForall ++ checkGenerate s maxDepth (currDepth+1) (Forall f) - where - appliedForall = checkGenerate (s ++ " " ++ show currDepth) maxDepth 0 (f (unpack (constant currDepth))) - -check :: Integer -> Prop -> Module() -check depth prop = do - let testSeq = Par (map Action (checkTwo (2^3-1) prop)) - - done <- run (reg 1 0) testSeq - - globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - (when done finish) - - globalTime <== globalTime.val + 1 - display "Time: " (globalTime.val) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 4)-b.==.b-a) - check (2^3-1) propSubComm - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Par_DifferentSizes_19-11.hs b/work/CheckOriginal/Old/Check_Par_DifferentSizes_19-11.hs deleted file mode 100644 index 884d69d..0000000 --- a/work/CheckOriginal/Old/Check_Par_DifferentSizes_19-11.hs +++ /dev/null @@ -1,50 +0,0 @@ --- Using prop a is more restrictive and generally wont work, this is a dead end - -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop a where - Assert :: (Bit 1) -> Prop (Bit 1) - Forall :: (Bits a, KnownNat (SizeOf a), Bits b, KnownNat (SizeOf b)) => (a -> Prop b) -> Prop a - - -applyToProp :: (Bits a, KnownNat (SizeOf a), Bits b, KnownNat (SizeOf b)) => Integer -> Prop a -> [Prop b] -applyToProp n (Forall (f :: (a -> Prop b))) = map f (map (\x -> unpack (constant x)) [0 .. n]) - -genInputs :: (Bits a, KnownNat (SizeOf a)) => Integer -> [Prop a] -> [Prop (Bit 1)] -genInputs _ [] = [] -genInputs n props@((Assert _):xs) = props -genInputs n props@((Forall _):xs) = - genInputs n (concat (map (applyToProp n) props)) - -displayProps :: (Bits a, KnownNat (SizeOf a)) => [Prop a] -> Action () -displayProps [] = finish -displayProps ((Assert p):props) = do - display "Test, result: " (p) - displayProps props - -checkTwo :: (Bits a, KnownNat (SizeOf a)) => Integer -> Prop a -> Action () -checkTwo depth prop = displayProps (genInputs depth [prop]) - -check :: (Bits a, KnownNat (SizeOf a)) => Integer -> Prop a -> Module() -check depth prop = do - let testSeq = (checkTwo (2^3-1) prop) - - --globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - testSeq - - --globalTime <== globalTime.val + 1 - --display "Time: " (globalTime.val) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 4)-b.==.b-a) - check (2^3-1) propSubComm - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Par_Simplified_12-11-19.hs b/work/CheckOriginal/Old/Check_Par_Simplified_12-11-19.hs deleted file mode 100644 index f26c4d1..0000000 --- a/work/CheckOriginal/Old/Check_Par_Simplified_12-11-19.hs +++ /dev/null @@ -1,48 +0,0 @@ -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, KnownNat (SizeOf a)) => (a -> Prop) -> Prop - - -applyToProp :: Integer -> Prop -> [Prop] -applyToProp n (Forall f) = map f (map (\x -> unpack (constant x)) [0 .. n]) - -genInputs :: Integer -> [Prop] -> [Prop] -genInputs _ [] = [] -genInputs n ((Assert p):xs) = ((Assert p):xs) -genInputs n ((Forall f):xs) = - genInputs n (concat (map (applyToProp n) ((Forall f):xs))) - -displayProps :: [Prop] -> Action () -displayProps [] = finish -displayProps ((Assert p):props) = do - display "Test, result: " (p) - displayProps props - -checkTwo :: Integer -> Prop -> Action () -checkTwo depth prop = displayProps (genInputs depth [prop]) - -check :: Integer -> Prop -> Module() -check depth prop = do - let testSeq = (checkTwo (2^3-1) prop) - - --globalTime :: Reg (Bit 32) <- makeReg 0 - - always do - testSeq - - --globalTime <== globalTime.val + 1 - --display "Time: " (globalTime.val) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 4)-b.==.b-a) - check (2^3-1) propSubComm - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Seq_Generator_20-11.hs b/work/CheckOriginal/Old/Check_Seq_Generator_20-11.hs deleted file mode 100644 index 400bf75..0000000 --- a/work/CheckOriginal/Old/Check_Seq_Generator_20-11.hs +++ /dev/null @@ -1,92 +0,0 @@ --- Generator allows for creating registers when walking Prop "list" and --- then just returning interfaces to (display, inc, reset and isfull) - -{-# LANGUAGE GADTs #-} - -import Blarney - -data Generator where - Empty :: Action () -> Generator - -- Display result - Gen :: Generator -> Action () -> Action () -> (Bit 1) -> Action () -> Generator - -- Gen below Display Increment Is full Reset - -data Prop where - Assert :: (Bit 1) -> Prop - Forall :: (Bits a, KnownNat (SizeOf a)) => (a -> Prop) -> Prop - -displayProp :: Generator -> Action () -displayProp (Empty disp) = disp -displayProp (Gen _ disp _ _ _) = disp - -displayPropWithValue :: (Bits a, KnownNat (SizeOf a)) => a -> Generator -> Action () -displayPropWithValue x g = do - display_ (pack x) " " - displayProp g - -isFinished :: Generator -> Bit 1 -isFinished (Empty disp) = 1 -isFinished (Gen g _ _ full _) = full .&. (isFinished g) - -checkSeq :: Prop -> Module (Generator) -checkSeq (Assert p) = do - return (Empty (display "Test result: " p)) -checkSeq (Forall f) = do - input <- makeReg (unpack 0) - g <- checkSeq (f (input.val)) - let displayValue = (displayPropWithValue (input.val) g) - let increment = (input <== (incReg (input.val))) - let full = (input.val === ones) - let reset = (input <== (unpack 0)) - return (Gen g displayValue increment full reset) - -incReg :: (Bits a, KnownNat (SizeOf a)) => a -> a -incReg x = unpack ((pack x) + 1) - -incrementGen :: Generator -> Action () -incrementGen (Empty _) = noAction -incrementGen (Gen g _ increment full reset) = do - if full - then do - reset - incrementGen g - else - increment - -check :: Prop -> Module(Bit 1) -check prop = do - g <- (checkSeq prop) - - globalTime :: Reg (Bit 32) <- makeReg 0 - testComplete :: Reg (Bit 1) <- makeReg 0 - always do - --(when (globalTime.val .==. 2000) finish) - globalTime <== globalTime.val + 1 - when (inv (testComplete.val)) do - testComplete <== isFinished g - incrementGen g - displayProp g - --display "Time: " (globalTime.val) - return (testComplete.val) - -firstHot :: KnownNat n => Bit n -> Bit n -firstHot x = x .&. ((inv x) .+. 1); - -top :: Module () -top = do - --let propSubComm = Forall \a -> Forall \b -> Assert ((a :: Bit 3)-b.==.b-a) - let prop_OneIsHot = Forall \x -> Assert (countOnes (firstHot (x :: Bit 4)) .==. ((x .==. 0) ? (0, 1))) - let prop_HotBitCommon = Forall \x -> Assert ((x :: Bit 4) .&. (firstHot x) .==. (firstHot x)) - let prop_HotBitFirst = Forall \x -> Assert ((x :: Bit 4) .&. ((firstHot x) - 1) .==. 0) - - t1Complete <- check prop_OneIsHot - t2Complete <- check prop_HotBitCommon - t3Complete <- check prop_HotBitFirst - - always do - when (t1Complete .&. t2Complete .&. t3Complete) do - finish - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Old/Check_Seq_Simple-12-11.19.hs b/work/CheckOriginal/Old/Check_Seq_Simple-12-11.19.hs deleted file mode 100644 index 87c2e0e..0000000 --- a/work/CheckOriginal/Old/Check_Seq_Simple-12-11.19.hs +++ /dev/null @@ -1,60 +0,0 @@ -{-# LANGUAGE GADTs #-} - -import Blarney - -data Prop n where - Assert :: (Bit 1) -> Prop n - Forall :: KnownNat n => (Bit n -> Prop n) -> Prop n - -calculateReqRegs :: Prop n -> Int -calculateReqRegs (Assert _) = 0 -calculateReqRegs (Forall f) = 1 + calculateReqRegs (f (constant 0)) - -displayProp :: KnownNat n => Prop n -> [Reg (Bit n)] -> Action () -displayProp (Assert p) [] = do - display "test result: " (p) -displayProp prop@(Assert _) (x:xs) = do - display_ (x.val) " " - displayProp prop xs - -checkSeq :: KnownNat n => Prop n -> [Reg (Bit n)] -> [Reg (Bit n)] -> Action () -checkSeq prop@(Assert _) _ usedRegs = displayProp prop usedRegs -checkSeq (Forall f) (reg:regs) usedRegs = checkSeq (f (reg.val)) regs (reg:usedRegs) -checkSeq (Forall f) [] usedRegs = checkSeq (f (constant 0)) [] usedRegs - -isFull :: (KnownNat n) => Reg (Bit n) -> Bit 1 -isFull x = (x.val + 1) .==. 0 - -incrementRegs :: (KnownNat n) => [Reg (Bit n)] -> Action () -incrementRegs [] = finish -incrementRegs (x:xs) = do - if (isFull x) - then do - x <== 0 - incrementRegs xs - else - x <== x.val + 1 - -check :: (KnownNat n) => Prop n -> Module() -check prop = do - regs :: [Reg (Bit n)] <- mapM makeReg (replicate (calculateReqRegs prop) 0) - let testSeq = (checkSeq prop regs []) - - globalTime :: Reg (Bit 32) <- makeReg 0 - always do - --(when (globalTime.val .==. 2000) finish) - globalTime <== globalTime.val + 1 - incrementRegs regs - testSeq - display "Time: " (globalTime.val) - - -top :: Module () -top = do - let propSubComm = Forall \a -> Forall \b -> Assert (a-b.==.a) :: Prop 3 - -- Displays results in reverse: ie. increment b to max, then a + 1 and b to max again etc. - check propSubComm - - -main :: IO () -main = writeVerilogTop top "top" "Out-Verilog/" diff --git a/work/CheckOriginal/Series.hs b/work/CheckOriginal/Series.hs deleted file mode 100644 index e64656e..0000000 --- a/work/CheckOriginal/Series.hs +++ /dev/null @@ -1,19 +0,0 @@ -module Check.Series where - -import Blarney - -type Series a = Integer -> [a] - -class Serial a where - series :: Series a - - -(\/) :: Series a -> Series a -> Series a -s1 \/ s2 = \d -> s1 d ++ s2 d -(><) :: Series a -> Series b -> Series (a, b) -s1 >< s2 = \d -> [(x,y) | x <- s1 d, y <- s2 d] - - -instance (KnownNat a) => Serial (Bit a) where - series 0 = [constant 0] - series d = [new | d > 0, (prev) <- series (d-1), new <- [prev, (prev .|. (1 .<<. (constant (d-1) :: (Bit a))))]] \ No newline at end of file diff --git a/work/README.txt b/work/README.txt deleted file mode 100644 index 5ad3a8b..0000000 --- a/work/README.txt +++ /dev/null @@ -1,24 +0,0 @@ -BLARNEYCHECK ------------- - -An exhaustive property-based testing library for Blarney. Make sure to include -the 'blarney' folder in this directory: -$ git clone https://github.com/mn416/blarney.git - -The library resides in the 'Haskell' directory and can be imported in any Haskell code: -import BlarneyCheck - -Example modules and associated test benches are provided in the 'BuggySuite' folder. -These can be simulated using the following command: -$ ./simulate.sh BuggySuite/.hs - -Simulation requires GHC 8.6.5 and Verilator to be installed. The examples are also given -as synthesis ready in the corresponding 'CheckFPGA_' directory. Simply: -$ cd CheckFPGA_ -$ make - -This synthesizes the module and test bench. Synthesis requires Quartus to be installed -on the system. To program an FPGA with the test bench run: -$ make download-sof -$ nios2-terminal - diff --git a/work/blarney b/work/blarney deleted file mode 160000 index 2363982..0000000 --- a/work/blarney +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 23639829adc5a94f67ff549111547978db6806bb diff --git a/work/simulate.sh b/work/simulate.sh deleted file mode 100755 index 556a6a4..0000000 --- a/work/simulate.sh +++ /dev/null @@ -1,83 +0,0 @@ -#!/bin/bash - -# Parse filename to execute -FILE=${1?Error: no file given} -FILENAME=$(basename "$FILE") -FILEDIR=$(dirname "$FILE") -GHC="/opt/ghc/bin" -BLC="blarney/Scripts/blc" - -# Check log flags -if [[ $* == *--log* ]]; then -if [[ $* == *--eval* ]]; then - OUTDIR="Evaluation" -else - OUTDIR="Simulation" -fi -fi - -# Check for ghc -if ! [[ -d $GHC || -x "$(command -v ghc)" ]]; then - echo "GHC not found! Please install using the following commands (sudo):" - echo "add-apt-repository -y ppa:hvr/ghc && apt-get update && apt-get install -y ghc-8.6.5" - exit 1 -fi - -# Check for additional packages -pkgs='verilator' -if ! dpkg -s $pkgs >/dev/null 2>&1; then - echo "$pkgs not found! Please install before simulation. Eg:" - echo "apt-get install $pkgs" - exit 1 -fi - -# Check for BLARNEYCHECK_ROOT variable -if [ -z "$BLARNEYCHECK_ROOT" ]; then - export BLARNEYCHECK_ROOT="$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )" - echo "BLARNEYCHECK_ROOT not set, defaulting to $BLARNEYCHECK_ROOT" -fi - -# Check that blc is modified -if ! grep -q "BLARNEYCHECK_ROOT" "$BLARNEYCHECK_ROOT/$BLC"; then - echo "Modified Blarney blc script to include BLARNEYCHECK_ROOT" - sed -i -e 's/INC="\$BLARNEY_ROOT\/Haskell"/INC="\$BLARNEY_ROOT\/Haskell:\$BLARNEYCHECK_ROOT\/Haskell:\$BLARNEYCHECK_ROOT\/BuggySuite"/g' "$BLARNEYCHECK_ROOT/$BLC" -fi - -# Compile file -echo "Compiling: $FILE" -PATH="$GHC:$PATH" BLARNEY_ROOT="${BLARNEY_ROOT:-$BLARNEYCHECK_ROOT/blarney}" eval "$BLARNEYCHECK_ROOT/$BLC" $FILE - -cd $FILEDIR -# Check that compilation succeeded -EXECUTABLE=$(basename $FILENAME .hs) -if [ ! -f "./$EXECUTABLE" ]; then - echo "" - echo "File failed to compile!" - exit 1 -fi - -# Execute file to generate verilog -./$EXECUTABLE -VERILOG_DIR=(./*-Verilog/) -if [ -z "$VERILOG_DIR" ]; then - echo "" - echo "No verilog was generated!" - echo "Make sure that the main Haskell function is:" - echo "main = writeVerilogTop \"top\" \"-Verilog/\"" - exit 1 -fi - -cd $VERILOG_DIR -# Compile verilog to executable -make -s -echo "Executing $EXECUTABLE with result of:" -mkdir -p ../Results/$OUTDIR/$EXECUTABLE -if [ -z "$OUTDIR" ]; then - (time ./top | head -n -1) 2>&1 -else - (time ./top | head -n -1) 2>&1 | tee "../Results/$OUTDIR/$EXECUTABLE/output_$(date +"%Y_%d_%m_%H_%M_%S").txt" -fi - -cd .. -rm -f *.o *.hi "./$EXECUTABLE" -rm -rf $VERILOG_DIR