diff --git a/README.md b/README.md
index 69b60340f..c629b1e29 100644
--- a/README.md
+++ b/README.md
@@ -1,11 +1,23 @@
-# Horus 3D Scanner Firmware
-
-This firmware is written in C. Version 0.2.
+# Horus 3D Scanner Firmware for WAVGAT + ZUMSCAN boards
 
+This firmware is derived from Horus firmware v 2.0
 Derived from Grbl v0.9 by Jesús Arroyo (Mundo Reader S.L.)
-
 Grbl's lead developer is Simen Svale Skogsrud. Sonney Jeon (Chamnit) improved some parts of grbl.
 
+Firmware adds extra initialization code to setup WAVGAT boards. 
+It also should be compatible with generic arduino boards.
+
+This firmware get back some grbl features stripped out by Horus/Ciclop:
+- multiple axis support (X,Y,Z)
+- limit switches and homing
+- G0, G4 G Codes support
+
+So you can use this firmware with your experimental hardware.
+
+To use second stepper on ZUMSCAN shield with this firmware it is needed to rewire two pins on the shield board: 
+- desolder or cut pins 6,7 on ZUMSCAN shield so they not connected to arduino
+- wire 6->9, 7->10
+
 
 ## Features
 
@@ -14,13 +26,16 @@ Grbl's lead developer is Simen Svale Skogsrud. Sonney Jeon (Chamnit) improved so
 *   Laser modules control
 *   Analog sensor read
 *   Configuration interface with $ commands
+*   Up to 3 steppers
+*   Use limit switches
 
 The default baudrate is 115200.
 
 
 ## Implemented G Codes
 
-*   G1   - Angular movement
+*   G0,G1- Angular movement
+*   G4   - Dwell (delay)
 *   G50  - Reset all positions to zero
 *   M0   - Program pause
 *   M2   - Program end and reset
@@ -34,7 +49,20 @@ The default baudrate is 115200.
 
 ### Arduino
 
-Open *horus-fw.ino*, select your board and upload.
+Open *horus-fw.ino*, select your board
+
+Adjust configuration for your hardware:
+
+  - axis resolution (defaults.h, section DEFAULTS_HORUS)
+    For Ciclop hardware with Nema-17 stepper and x16 microstepping driver
+    DEFAULT_X_STEPS_PER_DEG 16\*200/360 // step/deg
+
+  - limit switches
+    cpu_map.h, section CPU_MAP_ATMEGA328P_ZUMSCAN: adjust limit switches pins. More detailed info in cpu_map.h
+    config.h: homing probe order and params HOMING_INIT_LOCK, HOMING_CYCLE_\*, N_HOMING_LOCATE_CYCLE
+
+
+Build and upload.
 
 ### Make
 
diff --git a/config.h b/config.h
index 5eb8898e0..e217ea907 100644
--- a/config.h
+++ b/config.h
@@ -51,7 +51,8 @@
 
 // Default cpu mappings. Grbl officially supports the Arduino Uno only. Other processor types
 // may exist from user-supplied templates or directly user-defined in cpu_map.h
-#define CPU_MAP_ATMEGA328P_HORUS // Arduino Uno CPU for Horus Project
+//#define CPU_MAP_ATMEGA328P_HORUS // Arduino Uno CPU for Horus Project
+#define CPU_MAP_ATMEGA328P_ZUMSCAN
 
 // Define runtime command special characters. These characters are 'picked-off' directly from the
 // serial read data stream and are not passed to the grbl line execution parser. Select characters
@@ -84,9 +85,10 @@
 // on separate pin, but homed in one cycle. Also, it should be noted that the function of hard limits 
 // will not be affected by pin sharing.
 // NOTE: Defaults are set for a traditional 3-axis CNC machine. Z-axis first to clear, followed by X & Y.
-#define HOMING_CYCLE_0 (1<<Z_AXIS)                // REQUIRED: First move Z to clear workspace.
-#define HOMING_CYCLE_1 ((1<<X_AXIS)|(1<<Y_AXIS))  // OPTIONAL: Then move X,Y at the same time.
+//#define HOMING_CYCLE_0 (1<<Z_AXIS)                // REQUIRED: First move Z to clear workspace.
+//#define HOMING_CYCLE_1 ((1<<X_AXIS)|(1<<Y_AXIS))  // OPTIONAL: Then move X,Y at the same time.
 // #define HOMING_CYCLE_2                         // OPTIONAL: Uncomment and add axes mask to enable
+#define HOMING_CYCLE_0 (1<<Y_AXIS)                // HORUS: X is turntable, homing not required. Home Y axis
 
 // Number of homing cycles performed after when the machine initially jogs to limit switches.
 // This help in preventing overshoot and should improve repeatability. This value should be one or 
diff --git a/cpu_map.h b/cpu_map.h
index 2206a3193..4f868047e 100644
--- a/cpu_map.h
+++ b/cpu_map.h
@@ -77,6 +77,66 @@
 
 #endif
 
+#ifdef CPU_MAP_ATMEGA328P_ZUMSCAN // Arduino Uno + ZUM Scan board
+
+  // Define laser pulse output pins. NOTE: All laser pins must be on the same port.
+  #define LASER_DDR       DDRD
+  #define LASER_PORT      PORTD
+  #define LASER1_BIT      2  // Uno Digital Pin 2
+  #define LASER2_BIT      3  // Uno Digital Pin 3
+  #define LASER3_BIT      4  // Uno Digital Pin 4
+  #define LASER4_BIT      5  // Uno Digital Pin 5
+  #define LASER_MASK      ((1<<LASER1_BIT)|(1<<LASER2_BIT)|(1<<LASER3_BIT)|(1<<LASER4_BIT)) // All step bits
+
+  // Define serial port pins and interrupt vectors.
+  #define SERIAL_RX     USART_RX_vect
+  #define SERIAL_UDRE   USART_UDRE_vect
+
+  // Define step pulse output pins. NOTE: All step bit pins must be on the same port.
+  #define STEP_DDR        DDRB
+  #define STEP_PORT       PORTB
+  #define X_STEP_BIT      4  // Uno Digital Pin 12
+  #define Y_STEP_BIT      2  // Uno Digital Pin 10 rewired from 7
+  #define STEP_MASK       ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)) // All step bits
+
+  // Define step direction output pins. NOTE: All direction pins must be on the same port.
+  #define DIRECTION_DDR     DDRB
+  #define DIRECTION_PORT    PORTB
+  #define X_DIRECTION_BIT   5  // Uno Digital Pin 13
+  #define Y_DIRECTION_BIT   0  // Uno Digital Pin 8
+  #define DIRECTION_MASK    ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)) // All direction bits
+
+  // Define stepper driver enable/disable output pin.
+  #define STEPPERS_DISABLE_DDR    DDRB
+  #define STEPPERS_DISABLE_PORT   PORTB
+  #define STEPPERS_DISABLE_BIT    1  // Uno Digital Pin 9 + rewired pin 6
+  #define STEPPERS_DISABLE_MASK   (1<<STEPPERS_DISABLE_BIT)
+
+  // Define homing/hard limit switch input pins and limit interrupt vectors. 
+  // NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (pinout).
+  // https://github.com/gnea/grbl/wiki/Wiring-Limit-Switches
+  
+  #define LIMIT_DDR        DDRB
+  #define LIMIT_PIN        PINB
+  #define LIMIT_PORT       PORTB
+//  #define X_LIMIT_BIT      1  // Uno Digital Pin 9
+  #define Y_LIMIT_BIT      3  // Uno Digital Pin 11
+  #define LIMIT_MASK       (1<<Y_LIMIT_BIT) //((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)) // All limit bits
+  #define LIMIT_INT        PCIE0  // Pin change interrupt enable pin
+  #define LIMIT_INT_vect   PCINT0_vect // PCINT0_vect - D8 to D13 (Port B); PCINT1_vect - A0 to A5; PCINT2_vect - D0 to D7 (Port D)
+  #define LIMIT_PCMSK      PCMSK0 // Pin change interrupt register
+
+  // Define probe switch input pin.
+  #define PROBE_DDR       DDRC
+  #define PROBE_PIN       PINC
+  #define PROBE_PORT      PORTC
+  #define PROBE_BIT       5  // Uno Analog Pin 5
+  #define PROBE_MASK      (1<<PROBE_BIT)
+
+#endif
+
+//----------------------------------------------------------------------------------------
+
 #ifdef CPU_MAP_ATMEGA328P // (Arduino Uno) Officially supported by Grbl.
 
   // Define serial port pins and interrupt vectors.
diff --git a/defaults.h b/defaults.h
index a21964859..9a6142613 100644
--- a/defaults.h
+++ b/defaults.h
@@ -34,21 +34,21 @@
 
 #ifdef DEFAULTS_HORUS
   // Grbl generic default settings. Should work across different machines.
-  #define DEFAULT_X_STEPS_PER_DEG 16/1.8 // step/deg
-  #define DEFAULT_Y_STEPS_PER_DEG 16/1.8 // step/deg
-  #define DEFAULT_Z_STEPS_PER_DEG 16/1.8 // step/deg
+  #define DEFAULT_X_STEPS_PER_DEG 16*11 // step/deg
+  #define DEFAULT_Y_STEPS_PER_DEG 16*200/32 // step/deg
+  #define DEFAULT_Z_STEPS_PER_DEG 16*200/360 // step/deg
   #define DEFAULT_X_MAX_RATE (180.0*60) // 180*60 deg/min = 180 deg/sec
-  #define DEFAULT_Y_MAX_RATE (180.0*60) // 180*60 deg/min = 180 deg/sec
+  #define DEFAULT_Y_MAX_RATE (150.0*60) // 180*60 deg/min = 180 deg/sec
   #define DEFAULT_Z_MAX_RATE (180.0*60) // 180*60 deg/min = 180 deg/sec
   #define DEFAULT_X_ACCELERATION (180.0*60*60) // 180*60*60 deg/min^2 = 180 deg/sec^2
   #define DEFAULT_Y_ACCELERATION (180.0*60*60) // 180*60*60 deg/min^2 = 180 deg/sec^2
   #define DEFAULT_Z_ACCELERATION (180.0*60*60) // 180*60*60 deg/min^2 = 180 deg/sec^2
   #define DEFAULT_X_MAX_TRAVEL 1080.0 // deg
-  #define DEFAULT_Y_MAX_TRAVEL 1080.0 // deg
+  #define DEFAULT_Y_MAX_TRAVEL 2000.0 // deg
   #define DEFAULT_Z_MAX_TRAVEL 1080.0 // deg
   #define DEFAULT_STEP_PULSE_MICROSECONDS 10
   #define DEFAULT_STEPPING_INVERT_MASK 0
-  #define DEFAULT_DIRECTION_INVERT_MASK ((1<<Y_AXIS)|(1<<Z_AXIS))
+  #define DEFAULT_DIRECTION_INVERT_MASK 0 // ((1<<Y_AXIS)|(1<<Z_AXIS))
   #define DEFAULT_STEPPER_IDLE_LOCK_TIME 25 // msec (0-254, 255 keeps steppers enabled)
   #define DEFAULT_STATUS_REPORT_MASK ((BITFLAG_RT_STATUS_MACHINE_POSITION)|(BITFLAG_RT_STATUS_WORK_POSITION))
   #define DEFAULT_JUNCTION_DEVIATION 0.02 // deg
@@ -57,11 +57,11 @@
   #define DEFAULT_AUTO_START 1 // true
   #define DEFAULT_INVERT_ST_ENABLE 0 // false
   #define DEFAULT_INVERT_LIMIT_PINS 0 // false
-  #define DEFAULT_SOFT_LIMIT_ENABLE 0 // false
-  #define DEFAULT_HARD_LIMIT_ENABLE 0  // false
-  #define DEFAULT_HOMING_ENABLE 0  // false
+  #define DEFAULT_SOFT_LIMIT_ENABLE 1 // false
+  #define DEFAULT_HARD_LIMIT_ENABLE 1  // false
+  #define DEFAULT_HOMING_ENABLE 1  // false
   #define DEFAULT_HOMING_DIR_MASK 0 // move positive dir
-  #define DEFAULT_HOMING_FEED_RATE 25.0 // mm/min
+  #define DEFAULT_HOMING_FEED_RATE 60.0 // mm/min
   #define DEFAULT_HOMING_SEEK_RATE 500.0 // mm/min
   #define DEFAULT_HOMING_DEBOUNCE_DELAY 250 // msec (0-65k)
   #define DEFAULT_HOMING_PULLOFF 1.0 // mm
diff --git a/gcode.c b/gcode.c
index 6d6511e53..3b4d8a70c 100644
--- a/gcode.c
+++ b/gcode.c
@@ -151,16 +151,24 @@ uint8_t gc_execute_line(char *line)
       case 'G':
         // Determine 'G' command and its modal group
         switch(int_value) {
-          case 1:
+          case 0: case 1:
             if (axis_command) { FAIL(STATUS_GCODE_AXIS_COMMAND_CONFLICT); } // [Axis word/command conflict]
             axis_command = AXIS_COMMAND_MOTION_MODE; 
-            gc_block.modal.motion = MOTION_MODE_LINEAR;
+            gc_block.modal.motion = int_value; // MOTION_MODE_LINEAR;
             word_bit = MODAL_GROUP_G1; 
             break;
+
+          case 4: // G4 Dwell
+            word_bit = MODAL_GROUP_G0;
+            gc_block.non_modal_command = NON_MODAL_DWELL; 
+            break;
+
           case 50:
             gc_block.non_modal_command = NON_MODAL_RESET_POSITION;
             break;
-          default: FAIL(STATUS_GCODE_UNSUPPORTED_COMMAND); // [Unsupported G command]
+
+          default: 
+            FAIL(STATUS_GCODE_UNSUPPORTED_COMMAND); // [Unsupported G command]
         }  
         if (mantissa > 0) { FAIL(STATUS_GCODE_COMMAND_VALUE_NOT_INTEGER); } // [Unsupported or invalid Gxx.x command]
         // Check for more than one command per modal group violations in the current block
@@ -203,10 +211,16 @@ uint8_t gc_execute_line(char *line)
            words (I,J,K,L,P,R) have multiple connotations and/or depend on the issued commands. */
         switch(letter){
           case 'F': word_bit = WORD_F; gc_block.values.f = value; break;
+          case 'P': word_bit = WORD_P; gc_block.values.p = value; break;
+          case 'S': word_bit = WORD_S; gc_block.values.s = value; break;
           case 'T': word_bit = WORD_T; gc_block.values.t = int_value; break; // gc.values.t = int_value;
           case 'X': word_bit = WORD_X; gc_block.values.xyz[X_AXIS] = value; axis_words |= (1<<X_AXIS); break;
-          /*case 'Y': word_bit = WORD_Y; gc_block.values.xyz[Y_AXIS] = value; axis_words |= (1<<Y_AXIS); break;
-          case 'Z': word_bit = WORD_Z; gc_block.values.xyz[Z_AXIS] = value; axis_words |= (1<<Z_AXIS); break;*/
+#ifdef Y_STEP_BIT
+          case 'Y': word_bit = WORD_Y; gc_block.values.xyz[Y_AXIS] = value; axis_words |= (1<<Y_AXIS); break;
+#endif
+#ifdef Z_STEP_BIT
+          case 'Z': word_bit = WORD_Z; gc_block.values.xyz[Z_AXIS] = value; axis_words |= (1<<Z_AXIS); break;
+#endif
           default: FAIL(STATUS_GCODE_UNSUPPORTED_COMMAND);
         } 
         
diff --git a/lgtx8p.h b/lgtx8p.h
new file mode 100644
index 000000000..b15c841f6
--- /dev/null
+++ b/lgtx8p.h
@@ -0,0 +1,567 @@
+/*
+**
+** Copyright (c) 2013, 	LogicGreen techologies
+** All rights reserved.
+**
+** project  : LGT8F328PBSPPrj
+** filename : lgt8f328p_spec.h
+** version  : 1.0
+** date     : Feb 01, 2017
+
+VERSION HISTORY:
+----------------
+Version 	: 1.0
+Date 		: Feb 01, 2017
+Revised by 	: LogicGreen Software Group
+Description : Original version.
+**
+*/
+
+#ifndef _LGT8F328P_SPEC_H_
+#define _LGT8F328P_SPEC_H_
+
+//----------------------------------------------------------------
+// DSU (Digital Signal Co-processor) Register Definition
+//----------------------------------------------------------------
+#define DSCR	(*((volatile unsigned char *)0x20))	
+#define	DSUEN	7
+#define	DSMM	6
+#define	DSD1	5
+#define	DSD0	4
+#define	DSN	2
+#define	DSZ	1
+#define	DSC	0
+
+#define DSIR	(*((volatile unsigned char *)0x21))	
+#define DSSD	(*((volatile unsigned char *)0x22))	
+
+#define DSDX	(*((volatile unsigned char *)0x30))	
+#define DSDY	(*((volatile unsigned char *)0x31))	
+
+#define DSAL	(*((volatile unsigned char *)0x58))	
+#define DSAH	(*((volatile unsigned char *)0x59))	
+
+//----------------------------------------------------------------
+// GPIO Group C Register Definition
+//----------------------------------------------------------------
+#define	PC7	7
+
+//----------------------------------------------------------------
+// GPIO Group E Register Definition
+//----------------------------------------------------------------
+#define IPINE	(*((volatile unsigned char *)0x2C))
+#define IDDRE	(*((volatile unsigned char *)0x2D))
+#define IPORTE	(*((volatile unsigned char *)0x2E))	
+
+#define EPINE	(*((volatile unsigned char *)0xA7))
+#define EDDRE	(*((volatile unsigned char *)0xA8))
+#define EPORTE	(*((volatile unsigned char *)0xA9))	
+
+//#define USE_EIO_EREG
+
+#ifdef USE_EIO_EREG
+#define PINE	EPINE
+#define DDRE	EDDRE
+#define PORTE	EPORTE
+#else
+#define PINE	IPINE
+#define DDRE	IDDRE
+#define PORTE	IPORTE
+#endif
+
+#define OCPUE	(*((volatile unsigned char *)0xE1))	
+
+#define	PE7	7
+#define	PE6	6
+#define	PE5	5
+#define	PE4	4
+#define	PE3	3
+#define	PE2	2
+#define	PE1	1
+#define	PE0	0
+
+//----------------------------------------------------------------
+// GPIO Group F Register Definition
+//----------------------------------------------------------------
+#define PINF	(*((volatile unsigned char *)0x32))
+#define DDRF	(*((volatile unsigned char *)0x33))
+#define PORTF	(*((volatile unsigned char *)0x34))	
+
+#define	PF7	7
+#define	PF6	6
+#define	PF5	5
+#define	PF4	4
+#define	PF3	3
+#define	PF2	2
+#define	PF1	1
+#define	PF0	0
+
+//----------------------------------------------------------------
+// SPI (Serial Periphral Interface) Register Definition
+//----------------------------------------------------------------
+#define SPFR	(*((volatile unsigned char *)0x39))	
+#define	RDFULL	7
+#define	RDEMPT	6
+#define	RDPTR1	5
+#define	RDPTR0	4
+#define	WRFULL	3
+#define	WREMPT	2
+#define	WRPTR1	1
+#define	WRPTR0	0
+
+// Bits of SPSR
+#define DUAL	2
+
+//----------------------------------------------------------------
+// AC0 (Analog Comparator 0) Register Definition
+//----------------------------------------------------------------
+#define C0SR	(*((volatile unsigned char *)0x50))	
+#define	C0D	7
+#define	C0BG	6
+#define	C0O	5
+#define	C0I	4
+#define	C0IE	3
+#define	C0IC	2
+#define	C0IS1	1
+#define	C0IS0	0
+
+#define C0XR	(*((volatile unsigned char *)0x51))	
+#define	C0OE	6
+#define	C0HSYE	5
+#define	C0PS0	4
+#define	C0WKE	3
+#define	C0FEN	2
+#define	C0FS1	1
+#define	C0FS0	0
+
+#define C0TR	(*((volatile unsigned char *)0x52))	
+
+//----------------------------------------------------------------
+// AC1 (Analog Comparator 1) Register Definition
+//----------------------------------------------------------------
+#define C1SR	(*((volatile unsigned char *)0x2F))	
+#define	C1D	7
+#define	C1BG	6
+#define	C1O	5
+#define	C1I	4
+#define	C1IE	3
+#define	C1IC	2
+#define	C1IS1	1
+#define	C1IS0	0
+
+#define C1XR	(*((volatile unsigned char *)0x3A))	
+#define	C1OE	6
+#define	C1HSYE	5
+#define	C1PS0	4
+#define	C1WKE	3
+#define	C1FEN	2
+#define	C1FS1	1
+#define	C1FS0	0
+
+#define C1TR	(*((volatile unsigned char *)0x5B))	
+
+//----------------------------------------------------------------
+// EEP (E2PROM Controller) Register Definition
+//----------------------------------------------------------------
+#define E2PDL	(*((volatile unsigned char *)0x40))	
+#define E2PDH	(*((volatile unsigned char *)0x5A))	
+
+#define E2PD0	(*((volatile unsigned char *)0x40))	
+#define E2PD1	(*((volatile unsigned char *)0x5A))	
+#define E2PD2	(*((volatile unsigned char *)0x57))	
+#define E2PD3	(*((volatile unsigned char *)0x5C))	
+
+#define	ECCR	(*((volatile unsigned char *)0x56))
+#define ECS	0
+#define	CP0	2
+#define	CP1	3
+#define	SWM	4
+#define ERN	5
+#define	EEN	6
+#define	EWEN	7
+
+//----------------------------------------------------------------
+// TC0 (Timer Counter 0) Register Definition
+//----------------------------------------------------------------
+#define TCCR0C	(*((volatile unsigned char *)0x49))
+#define DSX07	7
+#define DSX06	6
+#define DSX05	5
+#define DSX04	4
+#define DSX01	1
+#define DSX00	0
+
+#define DTR0	(*((volatile unsigned char *)0x4F))
+
+// Bits of TCCR0B
+#define OC0AS	5
+#define DTEN0 	4
+
+// Bits of TIFR0
+#define OC0A	7
+#define OC0B	6
+
+//----------------------------------------------------------------
+// TC1 (Timer Counter 1) Register Definition
+//----------------------------------------------------------------
+#define TCCR1D	(*((volatile unsigned char *)0x83))
+#define DSX17	7
+#define DSX16	6
+#define DSX15	5
+#define DSX14	4
+#define DSX11	1
+#define DSX10	0
+
+#define DTR1L	(*((volatile unsigned char *)0x8C))
+#define DTR1H	(*((volatile unsigned char *)0x8D))
+
+#define PSSR	(*((volatile unsigned char *)0xE2))
+#define PSS1	7
+#define PSR1	0
+
+#define TCKSR	(*((volatile unsigned char *)0xEC))
+#define TCKCSR	(*((volatile unsigned char *)0xEC))
+#define F2XEN	6
+#define TC2XF1	5
+#define TC2XF0	4
+#define TC2XS1	1
+#define TC2XS0	0
+
+// Bits of TCCR1C
+#define DOC1B	5
+#define DOC1A	4
+#define DTEN1	3
+
+// Bits of TIFR1
+#define OC1A	7
+#define OC1B	6
+
+//----------------------------------------------------------------
+// TC2 (Timer Counter 2) Register Definition
+//----------------------------------------------------------------
+
+// Bits of ASSR
+#define INTCK	7
+
+// Bits of TIFR2
+#define OC2A	7
+#define OC2B	6
+
+//----------------------------------------------------------------
+// TC3 (Timer Counter 3) Register Definition
+//----------------------------------------------------------------
+#define TIFR3	(*((volatile unsigned char *)0x38))	
+#define OC3A	7
+#define OC3B	6
+#define ICF3 	5
+#define OCF3C 	3
+#define OCF3B 	2
+#define OCF3A 	1
+#define TOV3 	0
+
+#define TIMSK3	(*((volatile unsigned char *)0x71))
+#define ICIE3 	5
+#define OCIE3C 	3
+#define OCIE3B 	2
+#define OCIE3A 	1
+#define TOIE3 	0
+
+#define TCCR3A	(*((volatile unsigned char *)0x90))
+#define COM3A1 	7
+#define COM3A0 	6
+#define COM3B1 	5
+#define COM3B0 	4
+#define COM3C1 	3
+#define COM3C0 	2
+#define WGM31 	1
+#define WGM30 	0
+
+#define TCCR3B	(*((volatile unsigned char *)0x91))
+#define ICNC3 	7
+#define ICES3 	6
+#define WGM33 	4
+#define WGM32 	3
+#define CS32 	2
+#define CS31 	1
+#define CS30 	0
+
+#define TCCR3C	(*((volatile unsigned char *)0x92))
+#define FOC3A 	7
+#define FOC3B 	6
+#define DOC31 	5
+#define DOC30 	4
+#define DTEN3 	3
+#define DOC32 	1
+#define FOC3C 	0
+
+#define TCCR3D	(*((volatile unsigned char *)0x93))
+#define DSX37	7
+#define DSX36	6
+#define DSX35	5
+#define DSX34	4
+#define DSX31	1
+#define DSX30	0
+
+#define TCNT3L	(*((volatile unsigned char *)0x94))
+#define TCNT3H	(*((volatile unsigned char *)0x95))
+
+#define ICR3L	(*((volatile unsigned char *)0x96))
+#define ICR3H	(*((volatile unsigned char *)0x97))
+
+#define OCR3A	(*((volatile unsigned char *)0x98))
+#define OCR3AL	(*((volatile unsigned char *)0x98))
+#define OCR3AH	(*((volatile unsigned char *)0x99))
+
+#define OCR3B	(*((volatile unsigned char *)0x9A))
+#define OCR3BL	(*((volatile unsigned char *)0x9A))
+#define OCR3BH	(*((volatile unsigned char *)0x9B))
+
+#define DTR3A	(*((volatile unsigned char *)0x9C))
+#define DTR3B	(*((volatile unsigned char *)0x9D))
+
+#define OCR3C	(*((volatile unsigned char *)0x9E))
+#define OCR3CL	(*((volatile unsigned char *)0x9E))
+#define OCR3CH	(*((volatile unsigned char *)0x9F))
+
+// Bits of PSSR
+#define PSS3	6
+#define PSR3	1
+
+//----------------------------------------------------------------
+// PCI (PIN Change Interrupt) Register Definition
+//----------------------------------------------------------------
+#define PCMSK3	(*((volatile unsigned char *)0x73))
+#define PCMSK4	(*((volatile unsigned char *)0x74))
+
+// Bits of PCICR
+#define PCIE4	4
+#define PCIE3	3
+
+// Bits of PCIFR
+#define PCIF4	4
+#define PCIF3	3
+
+//----------------------------------------------------------------
+// ADC (Analog to Digital Controller) Register Definition
+//----------------------------------------------------------------
+
+// bit of ADCSRB
+#define ICTL	4
+
+#define ADCSRC	(*((volatile unsigned char *)0x7D))
+#define OFEN	7
+#define OFSF	6
+#define SPN	5
+#define AMEN	4
+#define SPD	2
+#define DIFS	1
+#define ADTM	0
+
+#define OFR0	(*((volatile unsigned char *)0xA3))
+#define OFR1	(*((volatile unsigned char *)0xA4))
+
+#define ADT0L	(*((volatile unsigned char *)0xA5))
+#define ADT0H	(*((volatile unsigned char *)0xA6))
+
+#define ADT1L	(*((volatile unsigned char *)0xAA))
+#define ADT1H	(*((volatile unsigned char *)0xAB))
+
+#define ADMSC	(*((volatile unsigned char *)0xAC))
+#define AMOF	7
+#define AMFC3	3
+#define AMFC2	2
+#define AMFC1	1
+#define AMFC0	0
+
+#define ADCSRD	(*((volatile unsigned char *)0xAD))
+#define BGEN	7
+#define REFS2	6
+#define IVSEL1	5
+#define IVSEL0	4
+#define VDS2	2
+#define VDS1	1
+#define VDS0	0
+
+#define DAPCR	(*((volatile unsigned char *)0xDC))
+#define DAPEN	7
+#define GA1	6
+#define GA0	5
+#define DNS2	4
+#define DNS1	3
+#define DNS0	2
+#define DPS1	1
+#define DPS0	0
+
+#define DAPTR	(*((volatile unsigned char *)0xDD))
+
+#define DAPTC	(*((volatile unsigned char *)0xDE))
+#define DAPTE	7
+
+// Bits of ADCSRB
+#define ACME01	7
+#define ACME00	6
+#define ACME11	5
+#define ACME10	4
+#define ACTS	3
+
+// Bits of DIDR0
+#define ADC7D	7
+#define ADC6D	6
+#define PE3D	7
+#define PE1D	6
+#define PC5D	5
+#define PC4D	4
+#define PC3D	3
+#define PC2D	2
+#define PC1D	1
+#define PC0D	0
+
+// Bits of DIDR1
+#define PE7D	7
+#define PE6D	6
+#define PE0D	5
+#define C0PD	4
+#define PF0D	3
+#define PC7D	2
+#define PD7D	1
+#define PD6D	0
+
+#define DIDR2	(*((volatile unsigned char *)0x76))
+#define PB5D	6
+
+//----------------------------------------------------------------
+// DAC (Digital to Analog Controller) Register Definition
+//----------------------------------------------------------------
+#define DACON	(*((volatile unsigned char *)0xA0))
+#define DACEN	3
+#define DAOE	2
+#define DAVS1	1
+#define DAVS0	0
+
+#define DALR	(*((volatile unsigned char *)0xA1))
+#define DAL0	(*((volatile unsigned char *)0xA1))
+
+//----------------------------------------------------------------
+// Config () Register Definition
+//----------------------------------------------------------------
+// Bits of MCUCR
+#define FWKEN	7
+#define FPDEN	6
+#define EXRFD	5
+#define IRLD	3
+#define IFAIL	2
+#define MWCE	0
+
+// Bits of MCUSR
+#define SWDD	7
+#define OCDRF	4
+
+// Bits of CLKPR
+#define WCE	7
+#define CLKOE1	6 
+#define CLKOE0	5
+#define CLKOE	5 
+
+#define VDTCR	(*((volatile unsigned char *)0x62))
+//#define WCE	7
+#define SWR	6
+#define VDTS2	4
+#define VDTS1	3
+#define VDTS0	2
+#define VDREN	1
+#define VDTEN	0
+
+#define PRR1	(*((volatile unsigned char *)0x65))
+#define	PRWDT	5
+#define	PRTC3	3
+#define	PREFL	2
+#define	PRPCI	1
+
+#define RCMCAL	(*((volatile unsigned char *)0x66))
+#define RCKCAL	(*((volatile unsigned char *)0x67))
+
+#define IVBASE	(*((volatile unsigned char *)0x75))
+
+#define IOCWK	(*((volatile unsigned char *)0xAE))
+#define IOCD7
+#define IOCD6
+#define IOCD5
+#define IOCD4
+#define IOCD3
+#define IOCD2
+#define IOCD1
+#define IOCD0
+
+#define DPS2R	(*((volatile unsigned char *)0xAF))
+#define DPS2E	3
+#define LPRCE	2
+#define TOS1	1
+#define TOS0	0
+
+#define VCAL 	(*((volatile unsigned char *)0xC8))
+#define VCAL3	(*((volatile unsigned char *)0xCC))
+#define VCAL1	(*((volatile unsigned char *)0xCD))
+#define VCAL2	(*((volatile unsigned char *)0xCE))
+
+#define LDOCR	(*((volatile unsigned char *)0xCF))	
+//#define WCE	7
+#define PDEN	3
+#define VSEL2	2
+#define VSEL1	1
+#define VSEL0	0
+
+#define HDR	(*((volatile unsigned char *)0xE0))	
+#define HDR5	5
+#define HDR4	4
+#define HDR3	3
+#define HDR2	2
+#define HDR1	1
+#define HDR0	0
+
+#define PMX1	(*((volatile unsigned char *)0xED))
+#define C3AC	2
+#define C2BF7	1
+#define C2AF6	0
+
+#define PMX0	(*((volatile unsigned char *)0xEE))
+//#define WCE	7
+#define C1BF4	6
+#define C1AF5	5
+#define C0BF3	4
+#define C0AC0	3
+#define SSB1	2
+#define TXD6	1
+#define RXD5	0
+
+#define PMX2	(*((volatile unsigned char *)0xF0))
+#define IOCR	(*((volatile unsigned char *)0xF0))
+//#define WCE	7
+#define IOCE	7
+#define STSC1	6
+#define STSC0	5
+#define XIEN	2
+#define E6EN	1
+#define REFIOEN	1
+#define C6EN	0
+#define RSTIOEN	0
+
+#define PMCR	(*((volatile unsigned char *)0xF2))
+#define PMCE	7
+#define CLKFS	6
+#define CLKSS	5
+#define WCLKS	4
+#define WCES	4
+#define OSCKEN	3
+#define OSCMEN	2
+#define RCKEN	1
+#define RCMEN	0
+
+#define GUID0	(*((volatile unsigned char *)0xF3))
+#define GUID1	(*((volatile unsigned char *)0xF4))
+#define GUID2	(*((volatile unsigned char *)0xF5))
+#define GUID3	(*((volatile unsigned char *)0xF6))
+
+#endif
+/**********************************************************************************
+***	     	  			EOF					***									  	
+**********************************************************************************/ 
diff --git a/limits.c b/limits.c
new file mode 100644
index 000000000..75cbd9330
--- /dev/null
+++ b/limits.c
@@ -0,0 +1,307 @@
+/*
+  limits.c - code pertaining to limit-switches and performing the homing cycle
+  Part of Grbl v0.9
+
+  Copyright (c) 2012-2014 Sungeun K. Jeon
+
+  Grbl is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  Grbl is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Grbl.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/* 
+  This file is based on work from Grbl v0.8, distributed under the 
+  terms of the MIT-license. See COPYING for more details.  
+    Copyright (c) 2009-2011 Simen Svale Skogsrud
+    Copyright (c) 2012 Sungeun K. Jeon
+*/  
+  
+#include "system.h"
+#include "settings.h"
+#include "protocol.h"
+#include "planner.h"
+#include "stepper.h"
+#include "motion_control.h"
+#include "limits.h"
+#include "report.h"
+
+// Homing axis search distance multiplier. Computed by this value times the axis max travel.
+#define HOMING_AXIS_SEARCH_SCALAR  1.5 // Must be > 1 to ensure limit switch will be engaged.
+
+
+void limits_init() 
+{
+  LIMIT_DDR &= ~(LIMIT_MASK); // Set as input pins
+
+  if (bit_istrue(settings.flags,BITFLAG_INVERT_LIMIT_PINS)) {
+    LIMIT_PORT &= ~(LIMIT_MASK); // Normal low operation. Requires external pull-down.
+  } else {
+    LIMIT_PORT |= (LIMIT_MASK);  // Enable internal pull-up resistors. Normal high operation.
+  }
+
+  if (bit_istrue(settings.flags,BITFLAG_HARD_LIMIT_ENABLE)) {
+    LIMIT_PCMSK |= LIMIT_MASK; // Enable specific pins of the Pin Change Interrupt
+    PCICR |= (1 << LIMIT_INT); // Enable Pin Change Interrupt
+  } else {
+    limits_disable(); 
+  }
+  
+  #ifdef ENABLE_SOFTWARE_DEBOUNCE
+    MCUSR &= ~(1<<WDRF);
+    WDTCSR |= (1<<WDCE) | (1<<WDE);
+    WDTCSR = (1<<WDP0); // Set time-out at ~32msec.
+  #endif
+}
+
+
+void limits_disable()
+{
+  LIMIT_PCMSK &= ~LIMIT_MASK;  // Disable specific pins of the Pin Change Interrupt
+  PCICR &= ~(1 << LIMIT_INT);  // Disable Pin Change Interrupt
+}
+
+
+// This is the Limit Pin Change Interrupt, which handles the hard limit feature. A bouncing 
+// limit switch can cause a lot of problems, like false readings and multiple interrupt calls.
+// If a switch is triggered at all, something bad has happened and treat it as such, regardless
+// if a limit switch is being disengaged. It's impossible to reliably tell the state of a 
+// bouncing pin without a debouncing method. A simple software debouncing feature may be enabled 
+// through the config.h file, where an extra timer delays the limit pin read by several milli-
+// seconds to help with, not fix, bouncing switches.
+// NOTE: Do not attach an e-stop to the limit pins, because this interrupt is disabled during
+// homing cycles and will not respond correctly. Upon user request or need, there may be a
+// special pinout for an e-stop, but it is generally recommended to just directly connect
+// your e-stop switch to the Arduino reset pin, since it is the most correct way to do this.
+#ifndef ENABLE_SOFTWARE_DEBOUNCE
+  ISR(LIMIT_INT_vect) // DEFAULT: Limit pin change interrupt process. 
+  {
+    // Ignore limit switches if already in an alarm state or in-process of executing an alarm.
+    // When in the alarm state, Grbl should have been reset or will force a reset, so any pending 
+    // moves in the planner and serial buffers are all cleared and newly sent blocks will be 
+    // locked out until a homing cycle or a kill lock command. Allows the user to disable the hard
+    // limit setting if their limits are constantly triggering after a reset and move their axes.
+    if (sys.state != STATE_ALARM) { 
+      if (bit_isfalse(sys.execute,EXEC_ALARM)) {
+        mc_reset(); // Initiate system kill.
+        bit_true_atomic(sys.execute, (EXEC_ALARM | EXEC_CRIT_EVENT)); // Indicate hard limit critical event
+      }
+    }
+  }  
+#else // OPTIONAL: Software debounce limit pin routine.
+  // Upon limit pin change, enable watchdog timer to create a short delay. 
+  ISR(LIMIT_INT_vect) { if (!(WDTCSR & (1<<WDIE))) { WDTCSR |= (1<<WDIE); } }
+  ISR(WDT_vect) // Watchdog timer ISR
+  {
+    WDTCSR &= ~(1<<WDIE); // Disable watchdog timer. 
+    if (sys.state != STATE_ALARM) {  // Ignore if already in alarm state. 
+      if (bit_isfalse(sys.execute,EXEC_ALARM)) {
+        uint8_t bits = LIMIT_PIN;
+        // Check limit pin state. 
+        if (bit_istrue(settings.flags,BITFLAG_INVERT_LIMIT_PINS)) { bits ^= LIMIT_MASK; }
+        if (bits & LIMIT_MASK) {
+          mc_reset(); // Initiate system kill.
+          bit_true_atomic(sys.execute, (EXEC_ALARM | EXEC_CRIT_EVENT)); // Indicate hard limit critical event
+        }
+      }  
+    }
+  }
+#endif
+
+
+// Homes the specified cycle axes, sets the machine position, and performs a pull-off motion after
+// completing. Homing is a special motion case, which involves rapid uncontrolled stops to locate
+// the trigger point of the limit switches. The rapid stops are handled by a system level axis lock 
+// mask, which prevents the stepper algorithm from executing step pulses. Homing motions typically 
+// circumvent the processes for executing motions in normal operation.
+// NOTE: Only the abort runtime command can interrupt this process.
+// TODO: Move limit pin-specific calls to a general function for portability.
+void limits_go_home(uint8_t cycle_mask) 
+{
+  if (sys.abort) { return; } // Block if system reset has been issued.
+
+  // Initialize homing in search mode to quickly engage the specified cycle_mask limit switches.
+  bool approach = true;
+  float homing_rate = settings.homing_seek_rate;
+  uint8_t invert_pin, idx;
+  uint8_t n_cycle = (2*N_HOMING_LOCATE_CYCLE+1);
+  float target[N_AXIS];
+  
+  uint8_t limit_pin[N_AXIS], step_pin[N_AXIS];
+  float max_travel = 0.0;
+  for (idx=0; idx<N_AXIS; idx++) {  
+    // Initialize limit and step pin masks
+    limit_pin[idx] = get_limit_pin_mask(idx);
+    step_pin[idx] = get_step_pin_mask(idx);
+
+    // Determine travel distance to the furthest homing switch based on user max travel settings.
+    // NOTE: settings.max_travel[] is stored as a negative value.
+    if (max_travel > settings.max_travel[idx]) { max_travel = settings.max_travel[idx]; }
+  }
+  max_travel *= -HOMING_AXIS_SEARCH_SCALAR; // Ensure homing switches engaged by over-estimating max travel.
+  
+  plan_reset(); // Reset planner buffer to zero planner current position and to clear previous motions.
+  
+  do {
+    // Initialize invert_pin boolean based on approach and invert pin user setting.
+    if (bit_isfalse(settings.flags,BITFLAG_INVERT_LIMIT_PINS)) { invert_pin = approach; }
+    else { invert_pin = !approach; }
+
+    // Initialize and declare variables needed for homing routine.
+    uint8_t n_active_axis = 0;
+    uint8_t axislock = 0;
+        
+    for (idx=0; idx<N_AXIS; idx++) {
+      // Set target location for active axes and setup computation for homing rate.
+      if (bit_istrue(cycle_mask,bit(idx))) { 
+        n_active_axis++;
+        if (!approach) { target[idx] = -max_travel; }
+        else { target[idx] = max_travel; }
+      } else {
+        target[idx] = 0.0;
+      }
+
+      // Set target direction based on cycle mask
+      if (bit_istrue(settings.homing_dir_mask,bit(idx))) { target[idx] = -target[idx]; }
+      
+      // Apply axislock to the step port pins active in this cycle.
+      if (bit_istrue(cycle_mask,bit(idx))) { axislock |= step_pin[idx]; }
+    }      
+    homing_rate *= sqrt(n_active_axis); // [sqrt(N_AXIS)] Adjust so individual axes all move at homing rate.
+    sys.homing_axis_lock = axislock;
+  
+    // Perform homing cycle. Planner buffer should be empty, as required to initiate the homing cycle.
+    uint8_t limit_state;
+    
+    #ifdef USE_LINE_NUMBERS
+      plan_buffer_line(target, homing_rate, false, HOMING_CYCLE_LINE_NUMBER); // Bypass mc_line(). Directly plan homing motion.
+    #else
+      plan_buffer_line(target, homing_rate, false); // Bypass mc_line(). Directly plan homing motion.
+    #endif
+    
+    st_prep_buffer(); // Prep and fill segment buffer from newly planned block.
+    st_wake_up(); // Initiate motion
+    do {
+      // Check limit state. Lock out cycle axes when they change.
+      limit_state = LIMIT_PIN;
+      if (invert_pin) { limit_state ^= LIMIT_MASK; }
+      for (idx=0; idx<N_AXIS; idx++) {
+        if (axislock & step_pin[idx]) {
+          if (limit_state & limit_pin[idx]) { axislock &= ~(step_pin[idx]); }
+        }
+      }
+      sys.homing_axis_lock = axislock;
+      st_prep_buffer(); // Check and prep segment buffer. NOTE: Should take no longer than 200us.
+      // Check only for user reset. No time to run protocol_execute_runtime() in this loop.
+      if (sys.execute & EXEC_RESET) { protocol_execute_runtime(); return; }
+    } while (STEP_MASK & axislock);
+    
+    st_reset(); // Immediately force kill steppers and reset step segment buffer.
+    plan_reset(); // Reset planner buffer. Zero planner positions. Ensure homing motion is cleared.
+
+    delay_ms(settings.homing_debounce_delay); // Delay to allow transient dynamics to dissipate.
+
+    // Reverse direction and reset homing rate for locate cycle(s).
+    homing_rate = settings.homing_feed_rate;
+    approach = !approach;
+    
+  } while (n_cycle-- > 0);
+    
+  // The active cycle axes should now be homed and machine limits have been located. By 
+  // default, grbl defines machine space as all negative, as do most CNCs. Since limit switches
+  // can be on either side of an axes, check and set axes machine zero appropriately. Also,
+  // set up pull-off maneuver from axes limit switches that have been homed. This provides
+  // some initial clearance off the switches and should also help prevent them from falsely
+  // triggering when hard limits are enabled or when more than one axes shares a limit pin.
+  for (idx=0; idx<N_AXIS; idx++) {
+    // Set up pull off targets and machine positions for limit switches homed in the negative
+    // direction, rather than the traditional positive. Leave non-homed positions as zero and
+    // do not move them.
+    // NOTE: settings.max_travel[] is stored as a negative value.
+    if (cycle_mask & bit(idx)) {
+    
+      #ifdef HOMING_FORCE_SET_ORIGIN
+        sys.position[idx] = 0;  // Set axis homed location as axis origin
+        target[idx] = settings.homing_pulloff;  
+        if ( bit_isfalse(settings.homing_dir_mask,bit(idx)) ) { target[idx] = -target[idx]; }     
+      #else
+        if ( bit_istrue(settings.homing_dir_mask,bit(idx)) ) {
+          target[idx] = settings.homing_pulloff+settings.max_travel[idx];
+          sys.position[idx] = lround(settings.max_travel[idx]*settings.steps_per_deg[idx]);
+        } else {
+          target[idx] = -settings.homing_pulloff;
+          sys.position[idx] = 0;
+        }
+      #endif
+      
+    } else { // Non-active cycle axis. Set target to not move during pull-off. 
+      target[idx] = (float)sys.position[idx]/settings.steps_per_deg[idx];
+    }
+  }
+  plan_sync_position(); // Sync planner position to current machine position for pull-off move.
+  
+  #ifdef USE_LINE_NUMBERS
+    plan_buffer_line(target, settings.homing_seek_rate, false, HOMING_CYCLE_LINE_NUMBER); // Bypass mc_line(). Directly plan motion.
+  #else
+    plan_buffer_line(target, settings.homing_seek_rate, false); // Bypass mc_line(). Directly plan motion.
+  #endif
+  
+  // Initiate pull-off using main motion control routines. 
+  // TODO : Clean up state routines so that this motion still shows homing state.
+  sys.state = STATE_QUEUED;
+  bit_true_atomic(sys.execute, EXEC_CYCLE_START);
+  protocol_execute_runtime();
+  protocol_buffer_synchronize(); // Complete pull-off motion.
+  
+  // Set system state to homing before returning. 
+  sys.state = STATE_HOMING; 
+}
+
+
+// Performs a soft limit check. Called from mc_line() only. Assumes the machine has been homed,
+// the workspace volume is in all negative space, and the system is in normal operation.
+void limits_soft_check(float *target)
+{
+  uint8_t idx;
+  uint8_t soft_limit_error = false;
+  for (idx=0; idx<N_AXIS; idx++) {
+   
+    #ifdef HOMING_FORCE_SET_ORIGIN
+      // When homing forced set origin is enabled, soft limits checks need to account for directionality.
+      // NOTE: max_travel is stored as negative
+      if (bit_istrue(settings.homing_dir_mask,bit(idx))) {
+        if (target[idx] < 0 || target[idx] > -settings.max_travel[idx]) { soft_limit_error = true; }
+      } else {
+        if (target[idx] > 0 || target[idx] < settings.max_travel[idx]) { soft_limit_error = true; }
+      }
+    #else  
+      // NOTE: max_travel is stored as negative
+      if (target[idx] > 0 || target[idx] < settings.max_travel[idx]) { soft_limit_error = true; }
+    #endif
+    
+    if (soft_limit_error) {
+      // Force feed hold if cycle is active. All buffered blocks are guaranteed to be within 
+      // workspace volume so just come to a controlled stop so position is not lost. When complete
+      // enter alarm mode.
+      if (sys.state == STATE_CYCLE) {
+        bit_true_atomic(sys.execute, EXEC_FEED_HOLD);
+        do {
+          protocol_execute_runtime();
+          if (sys.abort) { return; }
+        } while ( sys.state != STATE_IDLE || sys.state != STATE_QUEUED);
+      }
+    
+      mc_reset(); // Issue system reset and ensure spindle and coolant are shutdown.
+      bit_true_atomic(sys.execute, (EXEC_ALARM | EXEC_CRIT_EVENT)); // Indicate soft limit critical event
+      protocol_execute_runtime(); // Execute to enter critical event loop and system abort
+      return;
+    }
+  }
+}
diff --git a/limits.h b/limits.h
new file mode 100644
index 000000000..6ccd70f20
--- /dev/null
+++ b/limits.h
@@ -0,0 +1,41 @@
+/*
+  limits.h - code pertaining to limit-switches and performing the homing cycle
+  Part of Grbl v0.9
+
+  Copyright (c) 2012-2014 Sungeun K. Jeon  
+
+  Grbl is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  Grbl is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Grbl.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/* 
+  This file is based on work from Grbl v0.8, distributed under the 
+  terms of the MIT-license. See COPYING for more details.  
+    Copyright (c) 2009-2011 Simen Svale Skogsrud
+*/  
+
+#ifndef limits_h
+#define limits_h 
+
+
+// Initialize the limits module
+void limits_init();
+
+void limits_disable();
+
+// Perform one portion of the homing cycle based on the input settings.
+void limits_go_home(uint8_t cycle_mask);
+
+// Check for soft limit violations
+void limits_soft_check(float *target);
+
+#endif
\ No newline at end of file
diff --git a/main.c b/main.c
index 354258e15..7254f824b 100644
--- a/main.c
+++ b/main.c
@@ -35,7 +35,105 @@
 #include "probe.h"
 #include "report.h"
 #include "ldr.h"
+#include "limits.h"
 
+// ----------- WAVGAT boards support ---------
+/* For WAVGAT boards the manufacturer/seller provide the URL to download board specific files
+ *  after installing this files you can select the right board in Arduino IDE (WAVGAT UNO R3) and use it normally
+ *  
+ *  But to compile Horus-FW you should edit 
+ *  hardware\wavgat\WAV8F\cores\lgt8f\wiring.c 
+ *  and comment out (disable) following functions:
+ *  ISR(TIMER0_OVF_vect)
+ *  unsigned long millis()
+ *  unsigned long micros()
+ *  void delay(unsigned long ms)
+ */
+ 
+#if defined(ARDUINO_AVR_LARDU_328E)
+
+#include "lgtx8p.h"
+#define NO_TIM0
+
+#define  INT_OSC 0
+#define EXT_OSC 1
+
+
+
+void sysClock(uint8_t mode)
+{
+	if(mode == EXT_OSC) {
+		// enable external crystal
+		GPIOR0 = PMCR | 0x04;
+		PMCR = 0x80;
+		PMCR = GPIOR0;
+		
+		// waiting for crystal stable
+		delay(20);
+
+		// switch to external crystal
+		GPIOR0 = (PMCR & 0x9f) | 0x20;
+		PMCR = 0x80;
+		PMCR = GPIOR0;
+
+		// set to right prescale
+		CLKPR = 0x80;
+		CLKPR = 0x00;	
+	} else if(mode == INT_OSC) {
+		// prescaler settings
+		CLKPR = 0x80;
+		CLKPR = 0x01;	
+
+		// switch to internal crystal
+		GPIOR0 = PMCR & 0x9f;
+		PMCR = 0x80;
+		PMCR = GPIOR0;
+
+		// disable external crystal
+		GPIOR0 = PMCR & 0xfb;
+		PMCR = 0x80;
+		PMCR = GPIOR0;
+	}
+}	
+
+void lgt8fx8x_init()
+{
+#if defined(__LGT8FX8E__)
+// store ivref calibration 
+	GPIOR1 = VCAL1;
+	GPIOR2 = VCAL2;
+
+#if defined(__LGT8F_SSOP20__)
+	GPIOR0 = PMXCR | 0x07;
+	PMXCR = 0x80;
+	PMXCR = GPIOR0;
+#endif
+
+// enable 1KB E2PROM 
+	ECCR = 0x80;
+	ECCR = 0x40;
+
+// clock source settings
+	if((VDTCR & 0x0C) == 0x0C) {
+		// switch to external crystal
+		sysClock(EXT_OSC);
+	} else {
+		CLKPR = 0x80;
+		CLKPR = 0x01;
+	}
+#else
+	// enable 32KRC for WDT
+	GPIOR0 = PMCR | 0x10;
+	PMCR = 0x80;
+	PMCR = GPIOR0;
+
+	// clock scalar to 16MHz
+	CLKPR = 0x80;
+	CLKPR = 0x01;
+#endif
+}
+
+#endif
 
 // Declare system global variable structure
 system_t sys; 
@@ -43,6 +141,10 @@ system_t sys;
 
 int main(void)
 {
+#if defined(ARDUINO_AVR_LARDU_328E)
+    lgt8fx8x_init();
+#endif
+
   // Initialize system upon power-up.
   serial_init();   // Setup serial baud rate and interrupts
   settings_init(); // Load grbl settings from EEPROM
@@ -76,6 +178,7 @@ int main(void)
     serial_reset_read_buffer(); // Clear serial read buffer
     gc_init(); // Set g-code parser to default state
     laser_init();
+    limits_init();
     probe_init();
     plan_reset(); // Clear block buffer and planner variables
     st_reset(); // Clear stepper subsystem variables.
@@ -89,6 +192,7 @@ int main(void)
     sys.execute = 0;
     if (bit_istrue(settings.flags,BITFLAG_AUTO_START)) { sys.auto_start = true; }
     else { sys.auto_start = false; }
+//    sys.soft_limit = false;
           
     // Start Grbl main loop. Processes program inputs and executes them.
     protocol_main_loop();
diff --git a/motion_control.c b/motion_control.c
index 8767bde70..83d7d550e 100644
--- a/motion_control.c
+++ b/motion_control.c
@@ -232,7 +232,7 @@ void mc_dwell(float seconds)
 }
 
 
-/*// Perform homing cycle to locate and set machine zero. Only '$H' executes this command.
+// Perform homing cycle to locate and set machine zero. Only '$H' executes this command.
 // NOTE: There should be no motions in the buffer and Grbl must be in an idle state before
 // executing the homing cycle. This prevents incorrect buffered plans after homing.
 void mc_homing_cycle()
@@ -267,7 +267,7 @@ void mc_homing_cycle()
 
   // If hard limits feature enabled, re-enable hard limits pin change register after homing cycle.
   limits_init();
-}*/
+}
 
 
 // Perform tool length probe cycle. Requires probe switch.
diff --git a/settings.c b/settings.c
index 0a9c39899..8991d88ba 100644
--- a/settings.c
+++ b/settings.c
@@ -257,11 +257,11 @@ uint8_t settings_store_global_setting(uint8_t parameter, float value) {
           settings.flags |= BITFLAG_SOFT_LIMIT_ENABLE; 
         } else { settings.flags &= ~BITFLAG_SOFT_LIMIT_ENABLE; }
         break;
-      /*case 21:
+      case 21:
         if (int_value) { settings.flags |= BITFLAG_HARD_LIMIT_ENABLE; }
         else { settings.flags &= ~BITFLAG_HARD_LIMIT_ENABLE; }
         limits_init(); // Re-init to immediately change. NOTE: Nice to have but could be problematic later.
-        break;*/
+        break;
       case 22:
         if (int_value) { settings.flags |= BITFLAG_HOMING_ENABLE; }
         else { 
@@ -314,9 +314,12 @@ void settings_init() {
 // Returns step pin mask according to Grbl internal axis indexing.
 uint8_t get_step_pin_mask(uint8_t axis_idx)
 {
-  /*if ( axis_idx == X_AXIS ) { return((1<<X_STEP_BIT)); }
+#ifdef Z_STEP_BIT
+  if ( axis_idx == Z_AXIS ) { return((1<<Z_STEP_BIT)); }
+#endif
+#ifdef Y_STEP_BIT
   if ( axis_idx == Y_AXIS ) { return((1<<Y_STEP_BIT)); }
-  return((1<<Z_STEP_BIT));*/
+#endif
   return((1<<X_STEP_BIT));
 }
 
@@ -324,17 +327,29 @@ uint8_t get_step_pin_mask(uint8_t axis_idx)
 // Returns direction pin mask according to Grbl internal axis indexing.
 uint8_t get_direction_pin_mask(uint8_t axis_idx)
 {
-  /*if ( axis_idx == X_AXIS ) { return((1<<X_DIRECTION_BIT)); }
+#ifdef Z_DIRECTION_BIT
+  if ( axis_idx == Z_AXIS ) { return((1<<Z_DIRECTION_BIT)); }
+#endif
+#ifdef Y_DIRECTION_BIT
   if ( axis_idx == Y_AXIS ) { return((1<<Y_DIRECTION_BIT)); }
-  return((1<<Z_DIRECTION_BIT));*/
+#endif
   return((1<<X_DIRECTION_BIT));
 }
 
-
-/*// Returns limit pin mask according to Grbl internal axis indexing.
+#ifdef LIMIT_PORT
+// Returns limit pin mask according to Grbl internal axis indexing.
 uint8_t get_limit_pin_mask(uint8_t axis_idx)
 {
+#ifdef X_LIMIT_BIT
   if ( axis_idx == X_AXIS ) { return((1<<X_LIMIT_BIT)); }
+#endif
+#ifdef Y_LIMIT_BIT
   if ( axis_idx == Y_AXIS ) { return((1<<Y_LIMIT_BIT)); }
+#endif
+#ifdef Z_LIMIT_BIT
   return((1<<Z_LIMIT_BIT));
-}*/
+#else
+  return 0;
+#endif
+}
+#endif
diff --git a/stepper.c b/stepper.c
index 6eb2193b9..2b3b7b9b7 100644
--- a/stepper.c
+++ b/stepper.c
@@ -382,28 +382,34 @@ ISR(TIMER1_COMPA_vect)
     if (st.exec_block->direction_bits & (1<<X_DIRECTION_BIT)) { sys.position[X_AXIS]--; }
     else { sys.position[X_AXIS]++; }
   }
+
+#ifdef Y_STEP_BIT
   #ifdef ADAPTIVE_MULTI_AXIS_STEP_SMOOTHING
     st.counter_y += st.steps[Y_AXIS];
   #else
     st.counter_y += st.exec_block->steps[Y_AXIS];
   #endif    
   if (st.counter_y > st.exec_block->step_event_count) {
-    /*st.step_outbits |= (1<<Y_STEP_BIT);
+    st.step_outbits |= (1<<Y_STEP_BIT);
     st.counter_y -= st.exec_block->step_event_count;
     if (st.exec_block->direction_bits & (1<<Y_DIRECTION_BIT)) { sys.position[Y_AXIS]--; }
-    else { sys.position[Y_AXIS]++; }*/
+    else { sys.position[Y_AXIS]++; }
   }
+#endif
+
+#ifdef Z_STEP_BIT
   #ifdef ADAPTIVE_MULTI_AXIS_STEP_SMOOTHING
     st.counter_z += st.steps[Z_AXIS];
   #else
     st.counter_z += st.exec_block->steps[Z_AXIS];
   #endif  
   if (st.counter_z > st.exec_block->step_event_count) {
-    /*st.step_outbits |= (1<<Z_STEP_BIT);
+    st.step_outbits |= (1<<Z_STEP_BIT);
     st.counter_z -= st.exec_block->step_event_count;
     if (st.exec_block->direction_bits & (1<<Z_DIRECTION_BIT)) { sys.position[Z_AXIS]--; }
-    else { sys.position[Z_AXIS]++; }*/
-  }  
+    else { sys.position[Z_AXIS]++; }
+  }
+#endif
 
   // During a homing cycle, lock out and prevent desired axes from moving.
   if (sys.state == STATE_HOMING) { st.step_outbits &= sys.homing_axis_lock; }   
diff --git a/system.c b/system.c
index 79f32a467..045f191aa 100644
--- a/system.c
+++ b/system.c
@@ -145,7 +145,7 @@ uint8_t system_execute_line(char *line)
         case 'H' : // Perform homing cycle [IDLE/ALARM]
           if (bit_istrue(settings.flags,BITFLAG_HOMING_ENABLE)) { 
             // Only perform homing if Grbl is idle or lost.
-            /*mc_homing_cycle();*/
+            mc_homing_cycle();
             if (!sys.abort) { system_execute_startup(line); } // Execute startup scripts after successful homing.
           } else { return(STATUS_SETTING_DISABLED); }
           break;
diff --git a/system.h b/system.h
index 6ef49526b..7f2896f66 100644
--- a/system.h
+++ b/system.h
@@ -78,12 +78,13 @@ typedef struct {
   uint8_t abort;                 // System abort flag. Forces exit back to main loop for reset.
   uint8_t state;                 // Tracks the current state of Grbl.
   volatile uint8_t execute;      // Global system runtime executor bitflag variable. See EXEC bitmasks.
-  uint8_t homing_axis_lock;
+  uint8_t homing_axis_lock;      // Locks axes when limits engage. Used as an axis motion mask in the stepper ISR.
   int32_t position[N_AXIS];      // Real-time machine (aka home) position vector in steps. 
                                  // NOTE: This may need to be a volatile variable, if problems arise.                             
   uint8_t auto_start;            // Planner auto-start flag. Toggled off during feed hold. Defaulted by settings.
   volatile uint8_t probe_state;   // Probing state value.  Used to coordinate the probing cycle with stepper ISR.
   int32_t probe_position[N_AXIS]; // Last probe position in machine coordinates and steps.
+//  uint8_t soft_limit; // Tracks soft limit errors for the state machine. (boolean)
 } system_t;
 extern system_t sys;