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Improve systolic array (#1735) Docs website #593: Commit 52c5635 pushed by calebmkim
October 11, 2023 00:18 5m 2s master
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October 11, 2023 00:18 5m 2s
Create IDL Backend (#1729) Docs website #592: Commit 062b9a8 pushed by nathanielnrn
October 10, 2023 16:12 4m 28s master
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October 10, 2023 16:12 4m 28s
Improve Static Inline (#1734) Docs website #591: Commit 746f6a8 pushed by calebmkim
October 10, 2023 00:17 4m 25s master
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October 10, 2023 00:17 4m 25s
[fud] Fix environment variables for real-FPGA runs (#1728) Docs website #590: Commit ecb7900 pushed by nathanielnrn
September 24, 2023 16:18 3m 42s master
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September 24, 2023 16:18 3m 42s
Dynamic Implementation of ReLU (#1727) Docs website #589: Commit f6bd3a0 pushed by calebmkim
September 22, 2023 13:47 4m 2s master
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September 22, 2023 13:47 4m 2s
Add Regular ReLU Post Op for Systolic Arrays (#1720) Docs website #588: Commit 590c194 pushed by calebmkim
September 11, 2023 16:09 3m 47s master
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September 11, 2023 16:09 3m 47s
Cleaner Systolic Array Code (#1716) Docs website #587: Commit 22a2e6b pushed by calebmkim
September 7, 2023 19:20 3m 23s master
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September 7, 2023 19:20 3m 23s
Revert "Move numeric_types.py from fud/verilator to calyx-py (#… Docs website #586: Commit 26a11b8 pushed by calebmkim
September 7, 2023 13:17 3m 55s master
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September 7, 2023 13:17 3m 55s
Move numeric_types.py from fud/verilator to calyx-py (#1715) Docs website #585: Commit 1edf3ec pushed by calebmkim
September 7, 2023 12:22 3m 22s master
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September 7, 2023 12:22 3m 22s
Builder: infer more widths (#1683) Docs website #584: Commit 865d1a1 pushed by anshumanmohan
September 6, 2023 22:21 3m 8s master
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September 6, 2023 22:21 3m 8s
Systolic Array MM and Post Op Separated into Separate Components (#1… Docs website #583: Commit ede694a pushed by calebmkim
September 1, 2023 15:21 3m 13s master
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September 1, 2023 15:21 3m 13s
version 0.6.0 Docs website #582: Commit 3958c2c pushed by rachitnigam
August 31, 2023 12:21 3m 5s master
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August 31, 2023 12:21 3m 5s
define ir::rrc to build RRCs (#1710) Docs website #581: Commit 40f54c8 pushed by rachitnigam
August 31, 2023 11:30 3m 8s master
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August 31, 2023 11:30 3m 8s
Remove calyx lib.rs so it does not expose any thing (#1711) Docs website #580: Commit 4ceff9c pushed by rachitnigam
August 31, 2023 11:29 3m 6s master
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August 31, 2023 11:29 3m 6s
Rename interp to cider (#1686) Docs website #579: Commit c68dbb9 pushed by rachitnigam
August 31, 2023 11:21 3m 47s master
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August 31, 2023 11:21 3m 47s
more expressive guard! macro (#1709) Docs website #578: Commit 8fd9902 pushed by rachitnigam
August 31, 2023 11:15 3m 4s master
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August 31, 2023 11:15 3m 4s
bump runt version (#1708) Docs website #577: Commit 6c152c2 pushed by rachitnigam
August 31, 2023 09:09 3m 16s master
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August 31, 2023 09:09 3m 16s
Bump dependent crates (#1707) Docs website #576: Commit 165c0ef pushed by rachitnigam
August 31, 2023 09:02 3m 4s master
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August 31, 2023 09:02 3m 4s
move backend code into separate dir (#1706) Docs website #575: Commit 4183f96 pushed by rachitnigam
August 30, 2023 13:47 3m 4s master
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August 30, 2023 13:47 3m 4s
add version information for the compiler (#1705) Docs website #574: Commit 22cfbb3 pushed by rachitnigam
August 30, 2023 06:37 2m 58s master
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August 30, 2023 06:37 2m 58s
allow trailing comma in attribute list (#1703) Docs website #573: Commit 74b4053 pushed by rachitnigam
August 30, 2023 06:22 3m 33s master
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August 30, 2023 06:22 3m 33s
generate calyx.undefined for undef ops (#1704) Docs website #572: Commit 54493c0 pushed by rachitnigam
August 30, 2023 06:19 3m 0s master
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August 30, 2023 06:19 3m 0s
[Cider] Patch ref-cell bug (#1695) Docs website #571: Commit d423b38 pushed by EclecticGriffin
August 25, 2023 18:35 2m 56s master
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August 25, 2023 18:35 2m 56s
Compile-invoke compiles ref cells as well (#1692) Docs website #570: Commit 4cc8b60 pushed by rachitnigam
August 24, 2023 17:33 4m 7s master
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August 24, 2023 17:33 4m 7s
Redesign ir::Rewriter interface (#1691) Docs website #569: Commit 7750acb pushed by rachitnigam
August 23, 2023 06:25 2m 48s master
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August 23, 2023 06:25 2m 48s
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