From 67305da40bab988c059dbfea97a7df117170c43e Mon Sep 17 00:00:00 2001
From: Matt Hofmann <47065711+matth2k@users.noreply.github.com>
Date: Thu, 14 Mar 2024 10:50:37 -0400
Subject: [PATCH] Make inline prim input type explicit (#1970)

* make inline prim input type explicit

* update tests

---------

Co-authored-by: Rachit Nigam <rachit.nigam12@gmail.com>
---
 calyx-backend/src/verilog.rs                      |  2 +-
 primitives/core.sv                                |  1 -
 tests/backend/verilog/big-const.expect            | 14 +++++++-------
 tests/backend/verilog/data-instance.expect        | 14 +++++++-------
 .../verilog/memory-with-external-attribute.expect | 15 +++++++--------
 5 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
index 742a8b9e28..85bd9c5b5e 100644
--- a/calyx-backend/src/verilog.rs
+++ b/calyx-backend/src/verilog.rs
@@ -179,7 +179,7 @@ fn emit_prim_inline<F: io::Write>(
         // NOTE: The signature port definitions are reversed inside the component.
         match port.direction {
             ir::Direction::Input => {
-                write!(f, "   input")?;
+                write!(f, "   input wire")?;
             }
             ir::Direction::Output => {
                 write!(f, "   output")?;
diff --git a/primitives/core.sv b/primitives/core.sv
index 261571622f..7bcf11c2aa 100644
--- a/primitives/core.sv
+++ b/primitives/core.sv
@@ -6,7 +6,6 @@
  * - All parameter names must be SNAKE_CASE and all caps.
  * - Port names must be snake_case, no caps.
  */
-`default_nettype none
 
 module std_slice #(
     parameter IN_WIDTH  = 32,
diff --git a/tests/backend/verilog/big-const.expect b/tests/backend/verilog/big-const.expect
index 5e87d9cebb..022f6c0b44 100644
--- a/tests/backend/verilog/big-const.expect
+++ b/tests/backend/verilog/big-const.expect
@@ -18,7 +18,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -27,8 +27,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -37,10 +37,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );
diff --git a/tests/backend/verilog/data-instance.expect b/tests/backend/verilog/data-instance.expect
index d4fe0881d4..95e7b21744 100644
--- a/tests/backend/verilog/data-instance.expect
+++ b/tests/backend/verilog/data-instance.expect
@@ -18,7 +18,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -27,8 +27,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -37,10 +37,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );
diff --git a/tests/backend/verilog/memory-with-external-attribute.expect b/tests/backend/verilog/memory-with-external-attribute.expect
index e6e7ee1639..5f150a861c 100644
--- a/tests/backend/verilog/memory-with-external-attribute.expect
+++ b/tests/backend/verilog/memory-with-external-attribute.expect
@@ -244,7 +244,6 @@ endmodule
  * - All parameter names must be SNAKE_CASE and all caps.
  * - Port names must be snake_case, no caps.
  */
-`default_nettype none
 
 module std_slice #(
     parameter IN_WIDTH  = 32,
@@ -500,7 +499,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -509,8 +508,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -519,10 +518,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );