From 9311f5f2b8ddda19f000dc7cbc5739db294c8811 Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com> Date: Sat, 2 Mar 2024 20:36:42 -0500 Subject: [PATCH] [Calyx-FIRRTL] Initialize output ports (#1944) * First pass fix at setting output ports that are never used to invalid * Fix clippy errors * Quick debugging of port hack * Initialize output ports for FIRRTL and fix tests * Fix clippy error --- calyx-backend/src/firrtl.rs | 15 +++++++++++++-- tests/backend/firrtl/and-or-not-guard.expect | 6 ++++-- tests/backend/firrtl/basic-cell.expect | 8 ++++++-- tests/backend/firrtl/basic-guard.expect | 6 ++++-- tests/backend/firrtl/basic-program.expect | 4 ++++ tests/backend/firrtl/comparison-guard.expect | 6 ++++-- tests/backend/firrtl/or-guard.expect | 6 ++++-- tests/backend/firrtl/primitive-cells.expect | 8 ++++++-- tests/backend/firrtl/two-or-guards.expect | 6 ++++-- 9 files changed, 49 insertions(+), 16 deletions(-) diff --git a/calyx-backend/src/firrtl.rs b/calyx-backend/src/firrtl.rs index 7a743e49dd..c0b8d4ef04 100644 --- a/calyx-backend/src/firrtl.rs +++ b/calyx-backend/src/firrtl.rs @@ -7,6 +7,7 @@ use crate::{traits::Backend, VerilogBackend}; use calyx_ir::{self as ir, Binding, RRC}; use calyx_utils::{CalyxResult, Id, OutputFile}; use ir::Port; +use std::cell::RefCell; use std::collections::HashSet; use std::io; @@ -82,6 +83,8 @@ fn emit_component( comp: &ir::Component, f: &mut F, ) -> io::Result<()> { + let mut dst_set: HashSet = HashSet::new(); + writeln!(f, "{}module {}:", SPACING, comp.name)?; // Inputs and Outputs @@ -91,6 +94,15 @@ fn emit_component( emit_port(port, true, f)?; } + // write invalid statements for all output ports. + for port_ref in sig.ports.iter() { + let port = port_ref.as_ref(); + if port.borrow().direction == calyx_frontend::Direction::Input { + write_invalid_initialization(port, f)?; + dst_set.insert(port.borrow().canonical()); + } + } + // Add a COMPONENT START: anchor before any code in the component writeln!(f, "{}; COMPONENT START: {}", SPACING.repeat(2), comp.name)?; @@ -118,7 +130,6 @@ fn emit_component( } } - let mut dst_set: HashSet = HashSet::new(); // Emit assignments for asgn in &comp.continuous_assignments { match asgn.guard.as_ref() { @@ -293,7 +304,7 @@ fn get_port_string(port: &calyx_ir::Port, is_dst: bool) -> String { // variables that get set in assignments should get initialized to avoid the FIRRTL compiler from erroring. fn write_invalid_initialization( - port: &RRC, + port: &RefCell, f: &mut F, ) -> io::Result<()> { let default_initialization_str = "; default initialization"; diff --git a/tests/backend/firrtl/and-or-not-guard.expect b/tests/backend/firrtl/and-or-not-guard.expect index e5cfd4b30f..052e9b1d6f 100644 --- a/tests/backend/firrtl/and-or-not-guard.expect +++ b/tests/backend/firrtl/and-or-not-guard.expect @@ -9,10 +9,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> - ; COMPONENT START: main - done <= UInt(1) out is invalid ; default initialization out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) + ; COMPONENT START: main + done <= UInt(1) when and(or(not(cond), cond2), cond3): out <= in ; COMPONENT END: main diff --git a/tests/backend/firrtl/basic-cell.expect b/tests/backend/firrtl/basic-cell.expect index 7245170f08..a2d1b68464 100644 --- a/tests/backend/firrtl/basic-cell.expect +++ b/tests/backend/firrtl/basic-cell.expect @@ -12,6 +12,10 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> + out is invalid ; default initialization + out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) ; COMPONENT START: identity done <= UInt(1) out <= in @@ -22,12 +26,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> + done is invalid ; default initialization + done <= UInt(0) ; COMPONENT START: main inst id of identity inst invoke0_go of std_wire_1 inst invoke0_done of std_wire_1 - done is invalid ; default initialization - done <= UInt(0) when invoke0_done.out: done <= UInt(1) id.clk <= clk diff --git a/tests/backend/firrtl/basic-guard.expect b/tests/backend/firrtl/basic-guard.expect index c58d6e8d75..50fe256248 100644 --- a/tests/backend/firrtl/basic-guard.expect +++ b/tests/backend/firrtl/basic-guard.expect @@ -7,10 +7,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> - ; COMPONENT START: main - done <= UInt(1) out is invalid ; default initialization out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) + ; COMPONENT START: main + done <= UInt(1) when cond: out <= in ; COMPONENT END: main diff --git a/tests/backend/firrtl/basic-program.expect b/tests/backend/firrtl/basic-program.expect index caabab6c93..f5c2bb5fc6 100644 --- a/tests/backend/firrtl/basic-program.expect +++ b/tests/backend/firrtl/basic-program.expect @@ -6,6 +6,10 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> + out is invalid ; default initialization + out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) ; COMPONENT START: main done <= UInt(1) out <= in diff --git a/tests/backend/firrtl/comparison-guard.expect b/tests/backend/firrtl/comparison-guard.expect index 7bfdf4ba77..86d86a07a3 100644 --- a/tests/backend/firrtl/comparison-guard.expect +++ b/tests/backend/firrtl/comparison-guard.expect @@ -9,10 +9,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> - ; COMPONENT START: main - done <= UInt(1) out is invalid ; default initialization out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) + ; COMPONENT START: main + done <= UInt(1) when and(leq(var, var2), cond3): out <= in ; COMPONENT END: main diff --git a/tests/backend/firrtl/or-guard.expect b/tests/backend/firrtl/or-guard.expect index 80fd80b9a5..ed3c3c5a01 100644 --- a/tests/backend/firrtl/or-guard.expect +++ b/tests/backend/firrtl/or-guard.expect @@ -8,10 +8,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> - ; COMPONENT START: main - done <= UInt(1) out is invalid ; default initialization out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) + ; COMPONENT START: main + done <= UInt(1) when or(cond, cond2): out <= in ; COMPONENT END: main diff --git a/tests/backend/firrtl/primitive-cells.expect b/tests/backend/firrtl/primitive-cells.expect index c923963407..09ab043ab6 100644 --- a/tests/backend/firrtl/primitive-cells.expect +++ b/tests/backend/firrtl/primitive-cells.expect @@ -19,6 +19,10 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> + out is invalid ; default initialization + out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) ; COMPONENT START: plus_one inst add of std_add_32 done <= UInt(1) @@ -32,12 +36,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> + done is invalid ; default initialization + done <= UInt(0) ; COMPONENT START: main inst po of plus_one inst invoke0_go of std_wire_1 inst invoke0_done of std_wire_1 - done is invalid ; default initialization - done <= UInt(0) when invoke0_done.out: done <= UInt(1) invoke0_go.in <= go diff --git a/tests/backend/firrtl/two-or-guards.expect b/tests/backend/firrtl/two-or-guards.expect index 897ce97b53..91f7035c25 100644 --- a/tests/backend/firrtl/two-or-guards.expect +++ b/tests/backend/firrtl/two-or-guards.expect @@ -10,10 +10,12 @@ circuit main: input clk: Clock input reset: UInt<1> output done: UInt<1> - ; COMPONENT START: main - done <= UInt(1) out is invalid ; default initialization out <= UInt(0) + done is invalid ; default initialization + done <= UInt(0) + ; COMPONENT START: main + done <= UInt(1) when or(cond, cond2): out <= in when or(cond2, cond3):