[eDSL] Redesign the Standard Library #1929
Replies: 4 comments
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Tagging @sampsyo, @anshumanmohan, and @nathanielnrn for comments! |
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Seems like a cool idea! If we're just considering the sequential composition of groups, we could attempt to do something similar to how the |
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Agreed, it's a nice idea. I will just mention: as the eDSL gets Python-ier and richer, the experience of using it appears to stray further from the experience of writing straight Calyx. Eventually I can imagine having a Calyx user who can get really far using the eDSL, but then doesn't understand the .yx code that they've generated. Not sure if this is an issue! Re: the implementation, I'm pretty shaky on the existing black magic and can't really speak to this additional black magic 😅 I'd be happy to learn though! |
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This is great; I like it. One small note on the imagined syntax here: a = Memory.comb(32, 16) # Create a new combinational memory
b = Memory.comb(32, 16)
mul = Mult.seq() # A new sequential, non-pipelined multiplier I think we will need the initializations to know where to put the new cells. So instead of |
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The
calyx-py
standard currently provides very simple, primitive wrapper over AST construction. For example, thecomb_mem_d1
primitive is simply:My proposal is that we take inspiration from
calyx.builder
and design a new interface to the standard library where users can call nice, high-level methods to perform actions with library components. For example, this is the code we should be able to write:To make this is happen, there is a bunch of black-magic that needs to be handled in the background. Namely, each of these high-level operators like
.read
,.write
, and.apply
need to generate groups. The code above needs to implicitly sequence those generated groups to express the control program correctly. Let's break down the challenges into a couple of steps:Rich Primitive Interfaces
Borrowing ideas from
ControlBuilder
and the likes, we want to provideclass
definitions for primitives that have methods likeread
andapply
on them. This should be relatively straightforward: given some set of ports, generate a group and return the right ports for performing the remaining computation:Note that we inherit a base class
Memory
. The idea is that all memories inherit this class and provide a uniform interface. For example, it should be easy to:CombMem
andSeqMem
(although maybe we don't want this because of problems outlined in Deprecatestd_mem
#1261)Rich Control Builder
The next step, which I confess I don't have a full technical picture of, is designing new control operators like
repeat
and use them to provide even higher-level operators likecalyx.for
which automatically generating the indexing logic.The end-goal here is providing the ability to write high-level code to make Python DSLs more maintainable and usable.
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