Fix copy_done and send_done to be asserted at the correct time

[nathanielnrn]

Part of #1072

[nathanielnrn]

Need to understand how calyx programs in turn interact with rust to generate the code, i.e how can we find the correct number of cycles to go through. Also thinking about how to parametrically decide memory size

[sampsyo]

Here is where those signals are being defined in our Verilog generator:
https://github.com/cucapra/calyx/blob/33a2cf73b2c54ea014dddeea227fbc715a74648b/src/backend/xilinx/memory_axi.rs#L130-L138

It looks like the intent there is to say that the copying is done (copy_done is asserted) when we have copied memory_size elements, and analogously with sending. But memory_size is hard-coded to 32!
https://github.com/cucapra/calyx/blob/33a2cf73b2c54ea014dddeea227fbc715a74648b/src/backend/xilinx/memory_axi.rs#L105

Of course, we want to get this size from the actual memory in the Calyx program…

Seems like we will need to change the memory_module function to take this size information as a parameter. Fortunately, at the point where we call that, it looks like we have access to the actual memory itself:
https://github.com/cucapra/calyx/blob/ce7fce008d2978c187083e082632c3ffc02856a5/src/backend/xilinx/toplevel.rs#L55-L62